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Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Inventor:
Alidina; Mazhar M.
Address:
Allentown, PA
No. of patents:
9
Patents:












Patent Number Title Of Patent Date Issued
6819971 Fast computation of overflow flag in a bit manipulation unit November 16, 2004
A bit manipulation unit (BMU) scales and formats data and includes fast computation of the overflow flag. For fast computation the BMU's overflow flag is computed based on the input data and the shift amount. The overflow flag is calculated separately as either a LMV.sub.left for an
6801995 Method for optimally encoding a set of instruction codes for a digital processor having a plural October 5, 2004
A method of assigning unique instruction codes to instructions in an instruction set is disclosed. Such an encoded instruction set is also disclosed. Instructions are grouped according to the particular resources used, where all of the instructions in a group have one or more resource
6530014 Near-orthogonal dual-MAC instruction set architecture with minimal encoding bits March 4, 2003
A near-orthogonal dual-MAC instruction set is provided which implements virtually the entire functionality of the orthogonal instruction set of 272 commands using only 65 commands. The reduced instruction set is achieved by eliminating instructions based on symmetry with respect to the
6446193 Method and apparatus for single cycle processing of data associated with separate accumulators i September 3, 2002
A method and apparatus for reducing instruction cycles in a digital signal processor wherein the processor includes a multiplier unit, an adder, a memory, and at least one pair of first and second accumulators. The accumulators include respective guard, high and low parts. The method and
6175912 Accumulator read port arbitration logic January 16, 2001
A processor architecture having an accumulator register file with multiple shared read and/or write ports. Depending on the instruction, each port can be used to communicate with a different data source or destination.
6064714 Shifter capable of split operation May 16, 2000
A device for shifting data in a cascade multiplexer shifter allows the shifter to be used in a full-length mode or in a split mode where the shifter is divided into two equal halves with upper and lower half fields thereof respectively receiving individual data numbers. Each data number
5991785 Determining an extremum value and its index in an array using a dual-accumulation processor November 23, 1999
A data processor determines an overall extremum value of an input set of array data, with the input set of array data partitionable into a first set of array data and a second set of array data. The data processor includes a pair of compare-select circuits implemented in an adder as well
5987490 Mac processor with efficient Viterbi ACS operation and automatic traceback store November 16, 1999
A dual-MAC processor optimized so that two Viterbi ACS operations, including traceback bit storage, can be executed in two machine cycles is disclosed. The processor comprises a pair of adder arithmetic logic units connected to a common accumulator register bank and supporting full and
5889689 Hierarchical carry-select, three-input saturation March 30, 1999
There is disclosed a first adder subtractor combines the largest positive number or largest negative number capable of being represented by the number of bits in the datapath, as determined by the sign of an input to a second adder with a first input to generate a first potential sum. A










 
 
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