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Inventor:
Ajmera; Atul C.
Address:
Wappingers Falls, NY
No. of patents:
13
Patents:












Patent Number Title Of Patent Date Issued
7759206 Methods of forming semiconductor devices using embedded L-shape spacers July 20, 2010
A method of forming a semiconductor device that embeds an L-shaped spacer is provided. The method includes defining an L-shaped spacer on each side of a gate region of a substrate and embedding the L-shaped spacers in an oxide layer so that the oxide layer extends over a portion of the
7091128 Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs August 15, 2006
A method for forming a CMOS device in a manner so as to avoid dielectric layer undercut during a pre-silicide cleaning step is described. During formation of CMOS device comprising a gate stack on a semiconductor substrate surface, the patterned gate stack including gate dielectric b
6991979 Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs January 31, 2006
A method for forming a CMOS device in a manner so as to avoid dielectric layer undercut during a pre-silicide cleaning step is described. During formation of CMOS device comprising a gate stack on a semiconductor substrate surface, the patterned gate stack including gate dielectric b
6900092 Surface engineering to prevent epi growth on gate poly during selective epi processing May 31, 2005
The present invention provides a method of formed a nitrided surface layer atop a polysilicon gate electrode that inhibits the growth of an epi silicon layer thereon. Specifically, the method of the present invention includes the steps of: forming a polysilicon layer atop a gate dielectr
6642156 Method for forming heavy nitrogen-doped ultra thin oxynitride gate dielectrics November 4, 2003
A method for forming an ultra thin gate dielectric for an integrated circuit device is disclosed. In an exemplary embodiment of the invention, the method includes forming an initial nitride layer upon a substrate by rapidly heating the substrate in the presence of an ammonia (NH.sub.3)
6605521 Method of forming an oxide film on a gate side wall of a gate structure August 12, 2003
In order to prevent abnormal oxidation of the side wall of a polycide gate conductor layer in the oxidation heat treatment process after the RIE processing of the polycide gate conductor layer in a semiconductor memory cell, the heat treatment for oxidizing the side wall of the polycide
6566210 Method of improving gate activation by employing atomic oxygen enhanced oxidation May 20, 2003
The present invention provides a method of preparing a Si-based metal-insulator-semiconductor (MIS) transistor which prevents the polycrystalline grains of the gate conductor from getting significantly larger by reducing the thermal budget of the sidewall oxidation process. The therm
6566198 CMOS structure with non-epitaxial raised source/drain and self-aligned gate and method of manufa May 20, 2003
A CMOS structure and method of achieving self-aligned raised source/drain for CMOS structures on SOI without relying on selective epitaxial growth of silicon. In the method, CMOS structures are provided by performing sacrificial oxidation so that oxidation occurs on the surface of both t
6506649 Method for forming notch gate having self-aligned raised source/drain structure January 14, 2003
An innovative MOSFET having a raised source drain (RSD) is constructed prior to implanting source-drain dopants. The RSD structure thus built has a distinct advantage in that the offset from the RSD to the MOSFET channel is fully adjustable to minimize the overlap capacitance in the devi
6440807 Surface engineering to prevent EPI growth on gate poly during selective EPI processing August 27, 2002
The present invention provides a method of formed a nitrided surface layer atop a polysilicon gate electrode that inhibits the growth of an epi silicon layer thereon. Specifically, the method of the present invention includes the steps of: forming a polysilicon layer atop a gate dielectr
6437377 Low dielectric constant sidewall spacer using notch gate process August 20, 2002
A notched gate MOS device includes either an encapsulated low dielectric material or encapsulated air or a vacuum at the bottom of a notched gate. Due to the low dielectric constant at the site of interface between the gate and the source/drain, the capacitance loss at that site is s
6057220 Titanium polycide stabilization with a porous barrier May 2, 2000
A "porous barrier" is formed without formation of a discrete barrier layer by enriching grain boundaries of a body of polysilicon with nitrogen to inhibit thermal mobility of silicon species therealong. In a polycide gate/interconnect structure, the reduced mobility of silicon suppresses
6013583 Low temperature BPSG deposition process January 11, 2000
A process for the low temperature deposition of a thin film of borophosphosilicate glass ("BPSG") for use in semiconductor devices, such as DRAMs, is disclosed. The process includes utilizing R--OH groups as reagents to provide additional --OH groups so that an intermediate {Si(OH).s










 
 
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