| Patent Number |
Title Of Patent |
Date Issued |
| 8270323 |
Apparatus for, and method of, reducing noise in a communications system |
September 18, 2012 |
| A communication line having a plurality of twisted wire pairs connects a plurality of transmitters, one transmitter at each end of each twisted wire pair, with a plurality of receivers, one receiver at each end of each twisted wire pair. Each receiver receives a combination signal in |
| 8259787 |
High-speed decoder for a multi-pair gigabit transceiver |
September 4, 2012 |
| A method and a system for providing an input signal from a multiple decision feedback equalizer to a decoder based on a tail value and a subset of coefficient values received from a decision-feedback equalizer. A set of pre-computed values based on the subset of coefficient values is |
| 8229033 |
Digital signal processing based de-serializer |
July 24, 2012 |
| A DSP based SERDES performs compensation operations to support high speed de-serialization. A receiver section of the DSP based SERDES includes one or more ADCs and DSPs. The ADC operates to sample (modulated) analog serial data and to produce digitized serial data (digital representatio |
| 8201045 |
System and method for trellis decoding in a multi-pair transceiver system |
June 12, 2012 |
| A method and a system for decoding information signals encoded in accordance with a multi-state encoding scheme and transmitted over a multi-dimensional transmission channel by computing a distance of a received word from a codeword. One-dimensional (1D) input signals are processed i |
| 8189650 |
Startup protocol for high throughput communications systems |
May 29, 2012 |
| A startup protocol is provided for use in a communications system having a communications line with a master transceiver at a first end and a slave transceiver at a second end, each transceiver having a noise reduction system, a timing recovery system and at least one equalizer all c |
| 8179950 |
Startup protocol for high throughput communications systems |
May 15, 2012 |
| A startup protocol is provided for use in a communications system having a plurality of transceivers, one transceiver acting as a master and another transceiver acting as slave, each transceiver having a noise reduction system, a timing recovery system and at least one equalizer. The |
| 8139630 |
High-speed receiver architecture |
March 20, 2012 |
| A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-depe |
| 8111777 |
Method, apparatus and system for high-speed transmission on fiber optic channel |
February 7, 2012 |
| Multi-carrier modulation fiber optic systems constructed using a series of electrical carriers, modulating the data on the electrical carriers and combining the carriers to form a wideband signal. The wideband signal can then be intensity modulated on a laser and coupled to a fiber optic |
| 8077762 |
PHY control module for a multi-pair gigabit transceiver |
December 13, 2011 |
| A method for controlling operation of a multi-pair gigabit transceiver. The multi-pair gigabit transceiver comprises a Physical Layer Control module (PHY Control), a Physical Coding Sublayer module (PCS) and a Digital Signal Processing module (DSP). The PHY Control receives user-defi |
| 8031799 |
Multi-pair gigabit ethernet transceiver |
October 4, 2011 |
| Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characte |
| 8027410 |
Digital signal processing based de-serializer |
September 27, 2011 |
| A DSP based SERDES performs compensation operations to support high speed de-serialization. A receiver section of the DSP based SERDES includes one or more ADCs and DSPs. The ADC operates to sample (modulated) analog serial data and to produce digitized serial data (digital representatio |
| 7983569 |
High-speed transmission system for optical channels |
July 19, 2011 |
| A method and apparatus for transmission of data on bandwidth limited fiber optic channels. A multilevel signaling alphabet having multiple levels of optical intensity are used to transmit signals on optical channels. In order to counteract the decrease in signal to noise ratio result |
| 7936840 |
Demodulator for a multi-pair gigabit transceiver |
May 3, 2011 |
| A feedforward equalizer for equalizing a sequence of signal samples received by a receiver from a remote transmitter. The feedforward equalizer has a gain and is included in the receiver which includes a timing recovery module for setting a sampling phase and a decoder. The feedforwa |
| 7933341 |
System and method for high speed communications using digital signal processing |
April 26, 2011 |
| Various systems and methods related to equalization precoding in a communications channel are disclosed. In one implementation preceding is performed on signals transmitted over an optical channel. In one implementation preceding and decoding operations are performed in parallel to f |
| 7913127 |
Diagnostics of cable and link performance for a high-speed communication system |
March 22, 2011 |
| A method and system for performing diagnostic tests on a real-time system controlled by a state machine. A sequence of states recorded as the state machine operates is used to determine error conditions. The sequence of states is compared to expected sequences of states to determine what |
| 7881406 |
Method, apparatus and system for high-speed transmission on fiber optic channel |
February 1, 2011 |
| Multi-carrier modulation fiber optic systems constructed using a series of electrical carriers, modulating the data on the electrical carriers and combining the carriers to form a wideband signal. The wideband signal can then be intensity modulated on a laser and coupled to a fiber optic |
| 7852913 |
High-speed receiver architecture |
December 14, 2010 |
| A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-depe |
| 7844019 |
Timing recovery system for a multi-pair gigabit transceiver |
November 30, 2010 |
| A method and a timing recovery system for generating a set of clock signals in a system which includes a set of subsystems. Each of the subsystems includes an analog section. The set of clock signals includes a set of sampling clock signals. Each of the analog sections operates in ac |
| 7801241 |
Multi-pair gigabit Ethernet transceiver |
September 21, 2010 |
| Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characte |
| 7801240 |
Multi-pair gigabit ethernet transceiver |
September 21, 2010 |
| Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characte |
| 7792186 |
Multi-pair gigabit ethernet transceiver having a single-state decision feedback equalizer |
September 7, 2010 |
| Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characte |
| 7778313 |
PHY control module for a multi-pair gigabit transceiver |
August 17, 2010 |
| A method for controlling operation of a multi-pair gigabit transceiver. The multi-pair gigabit transceiver comprises a Physical Layer Control module (PHY Control), a Physical Coding Sublayer module (PCS) and a Digital Signal Processing module (DSP). The PHY Control receives user-defi |
| 7769101 |
Multi-pair gigabit ethernet transceiver |
August 3, 2010 |
| Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characte |
| 7733952 |
Multi-pair gigabit Ethernet transceiver having adaptive disabling of circuit elements |
June 8, 2010 |
| Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characte |
| 7729452 |
Method, apparatus and system for high-speed transmission on fiber optic channel |
June 1, 2010 |
| Multi-carrier modulation fiber optic systems constructed using a series of electrical carriers, modulating the data on the electrical carriers and combining the carriers to form a wideband signal. The wideband signal can then be intensity modulated on a laser and coupled to a fiber optic |
| 7711999 |
Diagnostics of cable and link performance for a high-speed communication system |
May 4, 2010 |
| A method and system for performing diagnostic tests on a real-time system controlled by a state machine. A sequence of states recorded as the state machine operates is used to determine error conditions. The sequence of states is compared to expected sequences of states to determine what |
| 7711077 |
System and method for high-speed decoding and ISI compensation in a multi-pair transceiver syste |
May 4, 2010 |
| A method and a system for providing ISI compensation to an input signal in a bifurcated manner. ISI compensation is provided in two stages, a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter, a second stage com |
| 7672368 |
PHY control module for a multi-pair gigabit transceiver |
March 2, 2010 |
| A control module for controlling convergence of cancellers, a decision feedback equalizer (DFE) and a timing recovery module. The control module includes a state machine operable to decouple the timing recovery module from the cancellers and the DFE while converging the cancellers and th |
| 7671681 |
Gigabit ethernet transceiver with analog front end |
March 2, 2010 |
| Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the s |
| 7656938 |
Demodulator for a multi-pair gigabit transceiver |
February 2, 2010 |
| A feedforward equalizer for equalizing a sequence of signal samples received by a receiver from a remote transmitter. The feedforward equalizer has a gain and is included in the receiver which includes a timing recovery module for setting a sampling phase and a decoder. The feedforwa |
| 7656827 |
Apparatus for, and method of, reducing noise in a communications system |
February 2, 2010 |
| A communication line having a plurality of twisted wire pairs connects a plurality of transmitters, one transmitter at each end of each twisted wire pair, with a plurality of receivers, one receiver at each end of each twisted wire pair. Each receiver receives a combination signal in |
| 7634001 |
Dynamic regulation of power consumption of a high-speed communication system |
December 15, 2009 |
| A method for dynamically regulating the power consumption of a high-speed integrated circuit which includes a multiplicity of processing blocks. A first metric and a second metric, which are respectively related to a first performance parameter and a second performance parameter of the |
| 7630434 |
High-speed decoder for a multi-pair gigabit transceiver |
December 8, 2009 |
| A method and a system for providing an input signal from a multiple decision feedback equalizer to a decoder based on a tail value and a subset of coefficient values received from a decision-feedback equalizer. A set of pre-computed values based on the subset of coefficient values is |
| 7598808 |
Gigabit ethernet transceiver with analog front end |
October 6, 2009 |
| Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the s |
| 7574135 |
Method, apparatus and system for high-speed transmission on fiber optic channel |
August 11, 2009 |
| Multi-carrier modulation fiber optic systems constructed using a series of electrical carriers, modulating the data on the electrical carriers and combining the carriers to form a wideband signal. The wideband signal can then be intensity modulated on a laser and coupled to a fiber optic |
| 7570701 |
Multi-pair gigabit ethernet transceiver |
August 4, 2009 |
| Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characte |
| 7492813 |
Startup protocol for high throughput communications systems |
February 17, 2009 |
| A startup protocol is provided for use in a communications system having a communications line with a master transceiver at a first end and a slave transceiver at a second end, each transceiver having a noise reduction system, a timing recovery system and at least one equalizer all c |
| 7480326 |
Channel diagnostic systems and methods |
January 20, 2009 |
| A system includes an adaptive filter coupled to a communication channel. The adaptive filter includes a set of adaptive filter coefficients. A memory stores a predetermined set of filter coefficient thresholds. The filter coefficient thresholds may be indicative of channel faults or a |
| 7471741 |
Method, apparatus and system for high-speed transmission on fiber optic channel |
December 30, 2008 |
| Multi-carrier modulation fiber optic systems constructed using a series of electrical carriers, modulating the data on the electrical carriers and combining the carriers to form a wideband signal. The wideband signal can then be intensity modulated on a laser and coupled to a fiber optic |
| 7453935 |
Multi-pair gigabit ethernet transceiver having decision feedback equalizer |
November 18, 2008 |
| Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characte |
| 7443910 |
PHY control module for a multi-pair gigabit transceiver |
October 28, 2008 |
| A method for controlling operation of a multi-pair gigabit transceiver. The multi-pair gigabit transceiver comprises a Physical Layer Control module (PHY Control), a Physical Coding Sublayer module (PCS) and a Digital Signal Processing module (DSP). The PHY Control receives user-defi |
| 7434134 |
System and method for trellis decoding in a multi-pair transceiver system |
October 7, 2008 |
| A method and a system for decoding information signals encoded in accordance with a multi-state encoding scheme and transmitted over a multi-dimensional transmission channel by computing a distance of a received word from a codeword. One-dimensional (1D) input signals are processed i |
| 7386038 |
Startup protocol for high throughput communications systems |
June 10, 2008 |
| A startup protocol is provided for use in a communications system having a plurality of transceivers, one transceiver acting as a master and another transceiver acting as slave, each transceiver having a noise reduction system, a timing recovery system and at least one equalizer. The |
| 7369608 |
Dynamic regulation of power consumption of a high-speed communication system |
May 6, 2008 |
| A method for dynamically regulating the power consumption of a high-speed integrated circuit which includes a multiplicity of processing blocks. A first metric and a second metric, which are respectively related to a first performance parameter and a second performance parameter of the |
| 7349492 |
Method, apparatus and system for high-speed transmission on fiber optic channel |
March 25, 2008 |
| Multi-carrier modulation fiber optic systems constructed using a series of electrical carriers, modulating the data on the electrical carriers and combining the carriers to form a wideband signal. The wideband signal can then be intensity modulated on a laser and coupled to a fiber optic |
| 7337375 |
Diagnostics of cable and link performance for a high-speed communication system |
February 26, 2008 |
| A method and system for performing diagnostic tests on a real-time system controlled by a state machine. A sequence of states recorded as the state machine operates is used to determine error conditions. The sequence of states is compared to expected sequences of states to determine what |
| 7336729 |
Digital signal processing based de-serializer |
February 26, 2008 |
| A DSP based SERDES performs compensation operations to support high speed de-serialization. A receiver section of the DSP based SERDES includes one or more ADCs and DSPs. The ADC operates to sample (modulated) analog serial data and to produce digitized serial data (digital representatio |
| 7336131 |
Gigabit ethernet transceiver with analog front end |
February 26, 2008 |
| Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the s |
| 7305029 |
Multi-pair gigabit ethernet transceiver |
December 4, 2007 |
| Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characte |
| 7263134 |
Ethernet transceiver with single-state decision feedback equalizer |
August 28, 2007 |
| Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characte |
