| Patent Number |
Title Of Patent |
Date Issued |
| 7543112 |
Efficient on-chip instruction and data caching for chip multiprocessors |
June 2, 2009 |
| The storage of data line in one or more L1 caches and/or a shared L2 cache of a chip multiprocessor is dynamically optimized based on the sharing of the data line. In one embodiment, an enhanced L2 cache directory entry associated with the data line is generated in an L2 cache directory |
| 7529911 |
Hardware-based technique for improving the effectiveness of prefetching during scout mode |
May 5, 2009 |
| One embodiment of the present invention provides a system that improves the effectiveness of prefetching during execution of instructions in scout mode. Upon encountering a non-data dependent stall condition, the system performs a checkpoint and commences execution of instructions in |
| 7475230 |
Method and apparatus for performing register file checkpointing to support speculative execution |
January 6, 2009 |
| One embodiment of the present invention provides a system that performs register file checkpointing to support speculative execution within a processor. During operation, the system commences speculative execution of a program from a point of speculation, at which the outcome of a long |
| 7472256 |
Software value prediction using pendency records of predicted prefetch values |
December 30, 2008 |
| Profile information can be used to target read operations that cause a substantial portion of misses in a program. A software value prediction technique that utilizes latency and is applied to the targeted read operations facilitates aggressive speculative execution without significa |
| 7434031 |
Execution displacement read-write alias prediction |
October 7, 2008 |
| RAW aliasing can be predicted with register bypassing based at least in part on execution displacement alias prediction. Repeated aliasing between read and write operations (e.g., within a loop), can be reliably predicted based on displacement between the aliasing operations. Perform |
| 7434004 |
Prefetch prediction |
October 7, 2008 |
| Predicting prefetch data sources for runahead execution triggering read operations eliminates the latency penalties of missing read operations that typically are not addressed by runahead execution mechanisms. Read operations that most likely trigger runahead execution are identified. |
| 7373482 |
Software-based technique for improving the effectiveness of prefetching during scout mode |
May 13, 2008 |
| One embodiment of the present invention provides a system that improves the effectiveness of prefetching during execution of instructions in scout mode. During operation, the system executes program instructions in a normal-execution mode. Upon encountering a condition which causes the |
| 7340567 |
Value prediction for missing read operations instances |
March 4, 2008 |
| Typically, missing read operations instances account for a small fraction of the operations instances of an application, but for nearly all of the performance degradation due to access latency. Hence, a small predictor structure maintains sufficient information for performing value p |
| 7185323 |
Using value speculation to break constraining dependencies in iterative control flow structures |
February 27, 2007 |
| One embodiment of the present invention provides a system that uses value speculation to break constraining dependencies in loops. The system operates by first identifying a loop within a computer program, and then identifying a dependency on a long-latency operation within the loop that |
| 7127592 |
Method and apparatus for dynamically allocating registers in a windowed architecture |
October 24, 2006 |
| One embodiment of the present invention provides a system that dynamically allocates physical registers in a windowed processor architecture. The system includes a physical register file and a register map that maps architectural registers defined within an executing program to physical |
| 7124254 |
Method and structure for monitoring pollution and prefetches due to speculative accesses |
October 17, 2006 |
| A method and structure for equipping a cache with information to enable the processor to track and report whether a given speculative access causes prefetches and/or pollutions of the cache. Two types of events are tracked in one of two different ways: first by counting/tracking prefetch |
| 6963823 |
Programmatic design space exploration through validity filtering and quality filtering |
November 8, 2005 |
| Design spaces for systems, including hierarchical systems, are programmatically validity filtered and quality filtered to produce validity sets and quality sets, reducing the number of designs to be evaluated in selecting a system design for a particular application. Validity filters |
| 6772106 |
Retargetable computer design system |
August 3, 2004 |
| An automatic and retargetable computer design system is using a combination of simulation and performance prediction to investigate a plurality of target computer systems. A high-level specification and a predetermined application are used by the computer design system to provide inputs |
| 6604067 |
Rapid design of memory systems using dilation modeling |
August 5, 2003 |
| A system is provided which simplifies and speeds up the process of designing a computer system by evaluating the components of the memory hierarchy for any member of a broad family of processors in an application-specific manner. The system uses traces produced by a reference process |
