| Patent Number |
Title Of Patent |
Date Issued |
| 6212648 |
Memory module having random access memories with defective addresses |
April 3, 2001 |
| The present invention provides a memory module having connective terminals and a plurality of random access memories connected through a first set of interconnections to the connective terminals. At least one of the random access memories has at least one defective address. The memory mo |
| 5708612 |
Semiconductor memory device |
January 13, 1998 |
| When a test mode signal is at an inactive level, a redundant cell column control circuit selects redundant cell column select signals. When the test mode signal is at an active level, the circuit selects a predetermined bit from the column select signal to output redundant cell colum |
| 5694369 |
Semiconductor memory device |
December 2, 1997 |
| A semiconductor memory device is proposed wherein dummy memory cells are provided at the most remote end of each word line with the object of enabling output of correct data despite the large or varying capacity between lines accompanying the trend to large capacity and despite varia |
| 5646895 |
Semiconductor memory device with bit line potential compensation circuits |
July 8, 1997 |
| The semiconductor memory device as static RAM disclosed comprises a memory cell array, a plurality of load circuits, and a plurality of bit line potential compensation circuits. Each of the bit line potential compensation circuits is a pseudo memory cell and is provided between each |
| 5535155 |
SRAM cell having load thin film transistors |
July 9, 1996 |
| In a static random access memory device including a flip-flop having first and second load thin film transistors whose drains are connected via first and second transfer bulk transistors to first and second bit lines, respectively, the second bit line is arranged over the first load thin |
| 5313434 |
Semiconductor memory device |
May 17, 1994 |
| A semiconductor memory device having a plurality of memory cells disposed in the form of a matrix with column switch circuits and an address transition detecting circuit. The column switch circuits are each provided for each of said bit line pairs with their one end connected to a co |
| 5293348 |
Random access memory device with columns of redundant memory cells distributed to memory cell ar |
March 8, 1994 |
| A random access memory device has at least one column of redundant memory cells for replacing a column of defective regular memory cells therewith, and a block address decoder circuit selects one of regular memory cell blocks on the basis of block address bits in so far as excellent regu |
