| Patent Number |
Title Of Patent |
Date Issued |
| 7467286 |
Executing partial-width packed data instructions |
December 16, 2008 |
| A method and apparatus are provided for executing packed data instructions. According to one aspect of the invention, a processor includes registers, a register renaming unit coupled to the registers, a decoder coupled to the register renaming unit, and a partial-width execution unit |
| 7430656 |
System and method of converting data formats and communicating between execution units |
September 30, 2008 |
| A method and system including transmitting data in an architectural format between execution units in a multi-type instruction set architecture and converting data received in the architectural format to an internal format and data output in the internal format to the architectural forma |
| 7216138 |
Method and apparatus for floating point operations and format conversion operations |
May 8, 2007 |
| A method and apparatus are described for converting a number from a floating point format to an integer format or from an integer format to a floating point format responsive to a control signal of a control signal format.Numbers are stored in the floating point format in a register of a |
| 7133040 |
System and method for performing an insert-extract instruction |
November 7, 2006 |
| An apparatus and method for performing an insert-extract operation on packed data using computer-implemented steps is described. In one embodiment, a first data operand having a data element is accessed. A second packed data operand having at least two data elements is then accessed. |
| 6970994 |
Executing partial-width packed data instructions |
November 29, 2005 |
| A method and apparatus for executing partial-width packed data instructions are discussed. The processor may include a plurality of registers, a register renaming unit, a decoder, and a partial-width execution unit. The register renaming unit provides an architectural register file to st |
| 6426746 |
Optimization for 3-D graphic transformation using SIMD computations |
July 30, 2002 |
| The present invention discloses a method and apparatus for optimizing three-dimensional (3-D) transformation on N vertices of a data object based on a transformation matrix of size K.times.K. The method comprises: storing coordinates of the N vertices in K data items, each of the K data |
| 6307553 |
System and method for performing a MOVHPS-MOVLPS instruction |
October 23, 2001 |
| An apparatus and method for performing a MOVHPS-MOVLPS operation on packed data using computer-implemented steps is described. In one embodiment, a first packed data operand having a pair of data elements is accessed. A second packed data operand having two pairs of data elements is then |
| 6233671 |
Staggering execution of an instruction by dividing a full-width macro instruction into at least |
May 15, 2001 |
| A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers re |
| 6115812 |
Method and apparatus for efficient vertical SIMD computations |
September 5, 2000 |
| An apparatus and method for performing vertical parallel operations on packed data is described. A first set of data operands and a second set of data operands are accessed. Each of these sets of data represents graphical data stored in a first format. The first set of data operands is |
| 6085312 |
Method and apparatus for handling imprecise exceptions |
July 4, 2000 |
| A method and apparatus for updating the architectural state in a system implementing staggered execution with multiple micro-instructions. According to one aspect of the invention, a method is provided in which a macro-instruction is decoded into a first and second micro-instructions. |
| 6041404 |
Dual function system and method for shuffling packed data elements |
March 21, 2000 |
| An apparatus and method for performing a shuffle operation on packed data using computer-implemented steps is described. In one embodiment, a first packed data operand having at least two data elements is accessed. A second packed data operand having at least two data elements is accesse |
| 6035318 |
Booth multiplier for handling variable width operands |
March 7, 2000 |
| A circuit for generating partial products for variable width multiplication operations is provided. According to an embodiment of the present invention, the circuit includes a plurality of partial product selector groups, each partial product selector group includes a plurality of pa |
