| Patent Number |
Title Of Patent |
Date Issued |
| 7516307 |
Processor for computing a packed sum of absolute differences and packed multiply-add |
April 7, 2009 |
| A method and apparatus is disclosed that computes multiple absolute differences from packed data and sums each one of the multiple absolute differences together to produce a result. According to one embodiment, a processor includes a decode unit to decode a packed sum of absolute dif |
| 7480360 |
Regulating a timing between a strobe signal and a data signal |
January 20, 2009 |
| A technique includes in response to a training mode, communicating between a device and a processor of a computer system over a data bit line of a bus. The technique includes based on the communication, regulating a timing between a strobe signal and a signal that propagates over the dat |
| 6918032 |
Hardware predication for conditional instruction path branching |
July 12, 2005 |
| An instruction associated with a condition is executed. In executing the instruction, a first operation designated by the instruction is performed to produce a first result, and a second operation is performed to produce a second result. Both the first result and the second result are |
| 6754812 |
Hardware predication for conditional instruction path branching |
June 22, 2004 |
| An instruction associated with a condition is executed when the condition is resolved. In executing the instruction, a first operation designated by the instruction is performed to produce a first result, and a second operation is performed to produce a second result. The first result or |
| 6718440 |
Memory access latency hiding with hint buffer |
April 6, 2004 |
| A request hint is issued prior to or while identifying whether requested data and/or one or more instructions are in a first memory. A second memory is accessed to fetch data and/or one or more instructions in response to the request hint. The data and/or instruction(s) accessed from |
| 6701414 |
System and method for prefetching data into a cache based on miss distance |
March 2, 2004 |
| A prefetcher to prefetch data for an instruction based on the distance between cache misses caused by the instruction. In an embodiment, the prefetcher includes a memory to store a prefetch table that contains one or more entries that include the distance between cache misses caused by |
| 6584549 |
System and method for prefetching data into a cache based on miss distance |
June 24, 2003 |
| A prefetcher to prefetch data for an instruction based on the distance between cache misses caused by the instruction. In an embodiment, the prefetcher includes a memory to store a prefetch table that contains one or more entries that include the distance between cache misses caused by |
| 6498605 |
Pixel span depth buffer |
December 24, 2002 |
| An efficient way to determine which objects in a 3D image are to be displayed and which are not because they are obscured by other displayed objects. Displayable elements are assigned depth values defining their relative perceived nearness to the viewer of the image. A comparison of |
| 6377970 |
Method and apparatus for computing a sum of packed data elements using SIMD multiply circuitry |
April 23, 2002 |
| A method and apparatus that adds each one of multiple elements of a packed data together to produce a result. According to one such a method and apparatus, each of a first set of portions of partial products is produced using a first set of partial product selectors in a multiplier, each |
| 6282554 |
Method and apparatus for floating point operations and format conversion operations |
August 28, 2001 |
| A floating point arithmetic apparatus for converting numbers between an integer format and a floating point format, wherein a conversion operation requires a greater data path width than a conversion operation. The apparatus comprises right shift circuitry that receives a number in the |
| 6269386 |
3X adder |
July 31, 2001 |
| A 3x adder for adding 2a to a, where a is a binary number, the binary numbers 2a and a partitioned so that 2a=(x.sup.k . . . x.sup.0) and a=(y.sup.k . . . y.sup.0)where x.sup.i and y.sup.i have the same size for each i=0, 1, . . . , k, where the 3x adder provides the group generate t |
| 6243803 |
Method and apparatus for computing a packed absolute differences with plurality of sign bits usi |
June 5, 2001 |
| A method and apparatus for computing a Packed Absolute Differences. According to one such method and apparatus, a third packed data having a third plurality of elements and the plurality of sign bits is produced, each of the third plurality of elements and the plurality of sign bits |
| 6192467 |
Executing partial-width packed data instructions |
February 20, 2001 |
| A method and apparatus are provided for executing scalar packed data instructions. According to one aspect of the invention, a processor includes a plurality of registers, a register renaming unit coupled to the plurality of registers, a decoder coupled to the register renaming unit, |
| 6122725 |
Executing partial-width packed data instructions |
September 19, 2000 |
| A method and apparatus are provided for executing scalar packed data instructions. According to one aspect of the invention, a processor includes a plurality of registers, a register renaming unit coupled to the plurality of registers, and a decoder coupled to the register renaming u |
