Disclosed are a system and method for providing fault isolation in a computer system including a central processing unit ("CPU") capable of issuing a signal to a memory to retrieve a requested instruction from the memory when the CPU is booted. The disclosed invention comprises an in
Disclosed are a circuit and method for learning attributes of computer memory (such as cacheability and writability) in a computer system. The circuit is coupled to a central processing unit ("CPU") and memory units within the computer system. The circuit is capable of retrieving an
A computer which carries its BIOS in a Flash EPROM. A UV-EPROM carries a redundant BIOS, which can be overlaid onto the BIOS address space by selection with a physical switch.The BIOS contains a small core software program, at the BIOS entry point, which checks BIOS integrity, and provid
