| Patent Number |
Title Of Patent |
Date Issued |
| 6795515 |
Method and apparatus for locating sampling points in a synchronous data stream |
September 21, 2004 |
| An apparatus and process for updating a sample time in a serial link which converts serial data in parallel data. A delay line stores multiple samples of at least two data bits received over the serial link. The contents of the delay line are matched so that they can be analyzed by a |
| 6661786 |
Service message system for a switching architecture |
December 9, 2003 |
| A service message system for a switching architecture including at least one Switch Fabric (10, 20) comprising a switch core (15, 25) located in a centralized building and a set of Switch Core Access Layer (SCAL) elements distributed in different physical areas for the attachment to the |
| 6563346 |
Phase independent frequency comparator |
May 13, 2003 |
| A method and circuit for comparing the frequencies of two clocks (clock.sub.-- 1 and clock.sub.-- 2), without taking into account their phase, is disclosed. Each clock is associated to a circular counter (100-1 and 100-2) which are initialized to different values, and the contents of |
| 6522269 |
System and method for a self-delineating serial link for very high-speed data communication inte |
February 18, 2003 |
| The system and method encodes a binary sequence of data bits into a sequence of ternary symbols and transmits the sequence of ternary symbols over a communication link. The encoding is performed so that no two consecutive symbols of the sequence are alike. The system and method assum |
| 5461641 |
Decimation filter for a sigma-delta converter and A/D converter using the same |
October 24, 1995 |
| A Decimation filter for converting a train of sigma-delta pulses S(i) in synchronism with a sigma-delta clock (fs) into a train of Pulse Coded Modulation (PCM) samples in accordance with the formula ##EQU1## where Cn is the sequence of the coefficients of the decimation filter wh |
| 5329553 |
Decimation filter for a sigma-delta converter and data circuit terminating equipment including t |
July 12, 1994 |
| A decimation filter for converting a received train of sigma-delta pulses in synchronism with a sigma-delta clock (fs) into a train of Pulse Code Modulation (PCM) samples having a PCM clock in accordance with the formula ##EQU1## includes a computer for computing one PCM sample from |
| 5315622 |
Data circuit terminating equipment (DCE) including timing arrangements circuits controlled by pr |
May 24, 1994 |
| Data Circuit Terminating Equipment (DCE) allows the connection of a Data Terminal Equipment (DTE) to a telecommunication line. The DCE includes timing elements for providing the DTE with any desired transmitter signal element timing and any desired receiver signal element timing. The tim |
| 5247546 |
Method and apparatus for automatic functional speed setting of a data circuit terminating equipm |
September 21, 1993 |
| A system implemented in a Data Circuit Terminating Equipment (DCE), interfacing between a user's data processing equipment and a digital network, comprises a detector for generating an Analog Carrier Detect (ACD) DCE internal signal as well as an Analog Squared Data (ASD) DCE interna |
| 5220327 |
Decimation filter in a sigma-delta analog-to-digtal converter |
June 15, 1993 |
| A decimation filter for converting a train of sigma-delta pulses S(i) in synchronism with a sigma-delta clock (fs) into a train of PCM samples which includes counters (321, 331, 341) driven by the sigma-delta clock (fs) and which is continuously incremented by one during N sigma-delta |
| 5210774 |
Adaptive equalization system and method for equalizing a signal in a DCE |
May 11, 1993 |
| An adaptive equalization system for allowing the equalization of a base-band line of a DCE within a predetermined range, includes an adaptive equalizer for continuously adapting its coefficients in accordance with a predetermined adaptive algorithm. The equalizer includes storage for a |
| 5196853 |
Sigma delta converter insensitive to asymmetrical switching times |
March 23, 1993 |
| Sigma-delta converter for converting an analog input signal into a sigma-delta code. The converter includes a threshold device (222) for generating an output and feedback signal, a filter receiving said analog input signal and said feedback signal from at least one feedback loop. The |
| 4941151 |
Predictive clock recovery circuit |
July 10, 1990 |
| A predictive clock extracting circuit having a first circuit for determining the duration between two consecutive transitions of a multilevel digital signal and a second circuit for generating an SPL pulse at half the duration after a third transition following on two consecutive pre |
| 4523322 |
Interface device for modems |
June 11, 1985 |
| An interface device for synchronizing an internally clocked modem and data terminal equipment (DTE) provided with their own clock circuits, each of said own terminal clock circuit providing an external clock signal (RC Ext). The interface includes a PLO generating a recovered clock signa |
