| Patent Number |
Title Of Patent |
Date Issued |
| 4513303 |
Self-aligned metal field effect transistor integrated circuit |
April 23, 1985 |
| A self-aligned metal field effect transistor is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal-to-metal spacing for field effect transistor integrated circuits. The insulation between the contacts and the metal is a pattern |
| 4424621 |
Method to fabricate stud structure for self-aligned metallization |
January 10, 1984 |
| A self-aligned metal process is described which achieves self-aligned metal silicon contacts and micron-to-submicron contact-to-contact and metal-to-metal spacing by use of the pattern of dielectric material having a thickness in the order of a micron or less. The pattern of recessed |
| 4359816 |
Self-aligned metal process for field effect transistor integrated circuits |
November 23, 1982 |
| A process is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal-to-metal spacing for field effect transistors. The insulation between the contacts and the metal is dielectric material having a thickness dimension about a micron |
| 4322883 |
Self-aligned metal process for integrated injection logic integrated circuits |
April 6, 1982 |
| A self-aligned metal process is described which achieves self-aligned metal to silicon contacts and sub-micron contact-to-contact and metal-to-metal spacing in the Integrated Injection Logic (I.sup.2 L) technology. The method involves providing a silicon body and then forming a first |
| 3992701 |
Non-volatile memory cell and array using substrate current |
November 16, 1976 |
| A non-volatile read mostly memory cell in a monocrystalline semiconductor body wherein the sensing of the information is achieved by measuring the substrate current. The cell includes spaced source and drain regions, a gate dielectric layer capable of trapping a charge, a substrate conta |
| 3962052 |
Process for forming apertures in silicon bodies |
June 8, 1976 |
| A process for forming holes with precisely controlled dimension and position in monocrystalline silicon wafers wherein the holes are fabricated with vertical sides. In the preferred process, both sides of the silicon body are masked, opposite registered openings made in the masking l |
| 3961355 |
Semiconductor device having electrically insulating barriers for surface leakage sensitive devic |
June 1, 1976 |
| A semiconductor device has a heavily doped semiconductor substrate with a lightly doped epitaxial layer overlying a surface of the substrate and of the same conductivity type as the substrate. Electrically insulating barriers extend from at least the surface of the epitaxial layer into t |
