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Fabrication methods of integrated semiconductor structure










Image Number 8 for United States Patent #8518780.

A method for manufacturing the integrated circuit device comprises providing a substrate having a first region, a second region, and a third region. A first dielectric layer is formed in the first region of the substrate. A second dielectric layer is formed in the second region and the third region. A sacrificial layer is formed over the first dielectric layer and the second dielectric layer. The sacrificial layer, the first dielectric layer, and the second dielectric layer are patterned to form a first gate stack, a second gate stack, and a third gate stack. An interlayer dielectric (ILD) layer is formed in between the first gate stack, the second gate stack, and the third gate stack. The second gate stack is removed to form an opening adjacent to the ILD layer and a third dielectric layer is formed in the opening.








 
 
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