Resources Contact Us Home
Semiconductor memory device having memory block configuration

Image Number 4 for United States Patent #8446765.

A semiconductor device includes a semiconductor substrate having first and second edge lines, address pads along the first edge line, and memory mats, each including normal memory blocks and a spare memory block. Each normal memory block has nonvolatile memory cells and is a unit of batch erase. The memory mats are arranged in a U-shaped area having a hollow portion facing the second edge line. The device includes column decoders arranged correspondingly to the memory mats, an analog/logic circuit arranged in the hollow portion, and a power supply pad arranged between the analog/logic circuit and the second edge line. The analog/logic circuit includes a charge pump circuit. The device further includes a first power supply interconnection supplying power supply voltage to the charge pump circuit from the power supply pad, and a second power supply interconnection supplying power supply voltage to the column decoder from the power supply pad.

  Recently Added Patents
Trimming circuit and semiconductor device
Image enhancement based on multiple frames and motion estimation
Purine compounds used as CB2 agonists
Code conversion apparatus, code conversion method, and computer product
Continuous geospatial tracking system and method
Image reconstruction iterative method
Method of treating cancer using a survivin inhibitor
  Randomly Featured Patents
Shift point strategy for hybrid electric vehicle transmission
Orthopedic implant system
Hydrogen elimination and thermal energy generation in water-activated chemical heaters
Method and central processing unit for processing encrypted software
Layered structures comprising particles, a dry binder and a foamable substance
Semiconductor device having no cracks in one or more layers underlying a metal line layer
Wellhead assembly for hydraulic pumping system
Automatic belt skirt for conveyor
Vacuum heat treatment furnace