Resources Contact Us Home
Semiconductor memory device having memory block configuration

Image Number 3 for United States Patent #8446765.

A semiconductor device includes a semiconductor substrate having first and second edge lines, address pads along the first edge line, and memory mats, each including normal memory blocks and a spare memory block. Each normal memory block has nonvolatile memory cells and is a unit of batch erase. The memory mats are arranged in a U-shaped area having a hollow portion facing the second edge line. The device includes column decoders arranged correspondingly to the memory mats, an analog/logic circuit arranged in the hollow portion, and a power supply pad arranged between the analog/logic circuit and the second edge line. The analog/logic circuit includes a charge pump circuit. The device further includes a first power supply interconnection supplying power supply voltage to the charge pump circuit from the power supply pad, and a second power supply interconnection supplying power supply voltage to the column decoder from the power supply pad.

  Recently Added Patents
Method and devices for handling access privileges
Low latency interrupt collector
Plants and seeds of hybrid corn variety CH817100
Electro-optical device, method of manufacturing the same, and electronic apparatus
Lubricating oil with enhanced protection against wear and corrosion
Multi-carrier operation for wireless systems
Image forming apparatus and control method therefor
  Randomly Featured Patents
Portable communication device
Soil mixer with scalloped cylinder
Lens retention means for vehicle lamp assembly
Semiconductor device with reduced noise propagation between circuit blocks
Web feed tractor for printer
Illuminating balloon catheter and method for using the catheter
Method for bulk coating using a plasma process
Embolic compositions
Multiconfiguration ionization source
Linkage of proteins to nucleic acids