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Semiconductor integrated circuit device with reduced cell size










Image Number 2 for United States Patent #8410526.

A semiconductor integrated circuit device with reduced cell size including a first tap formed in a first direction to supply a power-supply potential, a second tap formed in the first direction to supply a power-supply potential and positioned to confront the first tap in a second direction intersecting the first direction, and a standard cell formed between the first and second taps, a cell height (distance) between the center of the first tap and that of the second tap both in the second direction set to ((an integer+0.5).times.a wiring pitch of the second-layer wiring lines) or (an integer+0.25.times.a wiring pitch of the second-layer wiring lines.








 
 
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