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Power gateable retention storage element

Image Number 7 for United States Patent #8369133.

A method, electronic device, and system are provided in which data is stored in a gateable retention storage element. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus which includes a silicon chip. The method includes storing a data value in a storage element, wherein the storage element is at least one of a flip-flop, a latch or a register. The method also includes placing the storage element in a low power state comprising removing one or more existing connections between the actual ground node and at least one other component in the storage element. The method also includes maintaining the data value in the storage element subsequent to placing the storage element into the low power state. The electronic device includes a storage component for storing a data value. The electronic device also includes a pair of cross-coupled inverter components communicatively coupled to the storage component, the pair of cross-coupled inverter components being adapted to maintain the data value stored by the storage component subsequent to placing the storage component into a low power state and being adapted to maintain a connection with an actual ground node subsequent to placing the storage component into the low power state. The system includes an array of storage elements adapted to store data.

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