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Technique for exposing a placeholder material in a replacement gate approach by modifying a removal rate of stressed dielectric overlayers

Image Number 5 for United States Patent #8357575.

In a replacement gate approach, the sacrificial gate material is exposed on the basis of enhanced process uniformity, for instance during a wet chemical etch step or a CMP process, by forming a modified portion in the interlayer dielectric material by ion implantation. Consequently, the damaged portion may be removed with an increased removal rate while avoiding the creation of polymer contaminants when applying an etch process or avoiding over-polish time when applying a CMP process.

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