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LDPMOS structure for enhancing breakdown voltage and specific on resistance in biCMOS-DMOS process










Image Number 3 for United States Patent #8304830.

An LDPMOS structure having enhanced breakdown voltage and specific on-resistance is described, as is a method for fabricating the structure. A P-field implanted layer formed in a drift region of the structure and surrounding a lightly doped drain region effectively increases breakdown voltage while maintaining a relatively low specific on-resistance.








 
 
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