Resources Contact Us Home
On-chip identification circuit incorporating pairs of conductors, each having an essentially random chance of being shorted together as a result of process variations

Image Number 5 for United States Patent #8291357.

Disclosed are embodiments of on-chip identification circuitry. In one embodiment, pairs of conductors (e.g., metal pads, vias, lines) are formed within one or more metallization layers. The distance between the conductors in each pair is predetermined so that, given known across chip line variations, there is a random chance (i.e., an approximately 50/50 chance) of a short. In another embodiment different masks form first conductors (e.g., metal lines separated by varying distances and having different widths) and second conductors (e.g., metal vias separated by varying distances and having equal widths). The first and second conductors alternate across the chip. Due to the different separation distances and widths of the first conductors, the different separation distances of the second conductors and, random mask alignment variations, each first conductor can short to up to two second conductors. In each embodiment the resulting pattern of shorts and opens, can be used as an on-chip identifier or private key.

  Recently Added Patents
Stacked structure and stacked method for three-dimensional chip
Active element machine computation
Receiving security risk feedback from linked contacts due to a user's system actions and behaviors
Flash drive
Safety device and method for electric heating appliances
Signal activated molecular delivery
Stroboscopic light source for a transmitter of a large scale metrology system
  Randomly Featured Patents
Animal dressing tool
Method of manufacturing glass melt and method of manufacturing molded glass material
Locking and unlocking mechanism of post-curing inflator
Audio cassette
Double-walled paperboard cup
Photograph carrier
Composition and its use as a food supplement or for lowering lipids in serum
Inclined die cast shot sleeve system
Optical sensor membranes having improved barrier properties
Variable-gain differential input and output amplifier