Image Number 8 for United States Patent #8149884.
Disclosed is an apparatus comprising a jitter buffer that writes and reads packets transmitted via a packet network from a transmission node, a clock correction unit that obtains an inter-packet jitter, based on difference information between time stamp information at the time of reception of the packet on a receiving side and time stamp information attached to the packet at the time of transmission of the packet by a transmission node with regards to packets received before and after and obtains a transmission frequency and a PLL unit that receives frequency information from the clock correction unit and generates a clock of the frequency. A scheduler uses a frequency from the PLL unit as a transmission frequency to transmit a packet from the jitter buffer unit.
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