Resources Contact Us Home
Jitter buffer control method and communication apparatus

Image Number 8 for United States Patent #8149884.

Disclosed is an apparatus comprising a jitter buffer that writes and reads packets transmitted via a packet network from a transmission node, a clock correction unit that obtains an inter-packet jitter, based on difference information between time stamp information at the time of reception of the packet on a receiving side and time stamp information attached to the packet at the time of transmission of the packet by a transmission node with regards to packets received before and after and obtains a transmission frequency and a PLL unit that receives frequency information from the clock correction unit and generates a clock of the frequency. A scheduler uses a frequency from the PLL unit as a transmission frequency to transmit a packet from the jitter buffer unit.

  Recently Added Patents
Methods for determining decoding order in a MIMO system with successive interference cancellation
Digital IF demodulator for video applications
VGPU: a real time GPU emulator
Configuration method and system of complex network and configuration and management module of server resources
Battery-operated massager and soap dispensing wand
Methods and apparatus for adapting network characteristics in telecommunications systems
Jacket liner
  Randomly Featured Patents
Automated selection of generic blocking criteria
Liquid crystal display having vacuum layer for isolating heat
Wiper motor
Photographic element containing a stable aryloxypyrazolone coupler and process employing same
Fungicidal thienylurea derivatives
Surgical gown sleeve
Continuous adhesive applicator
Lubricating oil seal device for rotating shaft bearings
Method for producing a wound dressing
Pneumatic pressure control valve