Resources Contact Us Home
Jitter buffer control method and communication apparatus

Image Number 8 for United States Patent #8149884.

Disclosed is an apparatus comprising a jitter buffer that writes and reads packets transmitted via a packet network from a transmission node, a clock correction unit that obtains an inter-packet jitter, based on difference information between time stamp information at the time of reception of the packet on a receiving side and time stamp information attached to the packet at the time of transmission of the packet by a transmission node with regards to packets received before and after and obtains a transmission frequency and a PLL unit that receives frequency information from the clock correction unit and generates a clock of the frequency. A scheduler uses a frequency from the PLL unit as a transmission frequency to transmit a packet from the jitter buffer unit.

  Recently Added Patents
Display window with level of service graphical user interface
Plastic floor-wall transition methods, materials, and apparatus
Potentiometric-sensor chip, potentiometric assay, and assay kit
Photovoltaic system with integrated photovoltaic panel and battery
Light emitting device power supply circuit, and light emitting device driver circuit and control method thereof
Nonvolatile semiconductor memory device
Highly stable electrolytic water with reduced NMR half line width
  Randomly Featured Patents
Icon for a portion of a display screen
Precision loop voltage detector for subscriber line interface circuit applications
Cosmetic/dermatological compositions formulated as supple doughs
Frequency scanning automatic phase control system
Thermal container
Bubble generating device having a float connected thereto
Method for forming contact of semiconductor device
Floor grinding machine and grinding head unit therefor
Process and device for separation with variable-length chromatographic
Swimming flipper with blade and footwear structure