Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Test apparatus and test method










Image Number 16 for United States Patent #8149721.

There is provided a test apparatus for testing a device under test, including an obtaining section that obtains a packet sequence communicated between the test apparatus and the device under test, from a simulation environment for simulating an operation of the device under test, a packet communication program generating section that generates from the packet sequence a packet communication program for a test, where the packet communication program is to be executed by the test apparatus to communicate packets included in the packet sequence between the test apparatus and the device under test, and a testing section that executes the packet communication program to test the device under test by communicating the packets between the test apparatus and the device under test.








 
 
  Recently Added Patents
Face recognition through face building from two or more partial face images from the same face
Adaptive flow for thermal cooling of devices
Efficient implementation of hash algorithm on a processor
Collaborative data redundancy for configuration tracking systems
Reduction of HMF ethers with metal catalyst
Signal processing device and method for providing oscillating signal in the signal processing device
Providing multiple decode options for a system-on-chip (SoC) fabric
  Randomly Featured Patents
Online trading for the placement of advertising in media
Process for the preparation of cycloalkane-1,2-diones
Dispenser for plastic cards
Thin germanium oxynitride gate dielectric for germanium-based devices
Paper sizing and composition and method
Optical storage device and optical head having TES compensation shift signal compensation
Reversible shoe tongue
Method and apparatus for testing thin-film magnetic head
Structure for mounting cremorne lock and reinforcing member in vertical frame element constituting door or window leaf
Leveraging low-latency memory access