Image Number 16 for United States Patent #8132145.
A method used for supporting designing of a printed circuit board including a plurality of conductive layers having conductive areas to which a constant potential is applied, includes specifying conductive areas having a predetermined wiring from the conductive areas for each of the plurality of conductive layers, extracting areas that overlap each other in a planar view from the specified conductive areas, specifying an interlayer connection member that electrically connects at least two of the plurality of conductive layers in the extracted area, and clearly specifying an area within a predetermined distance from a center of the specified interlayer connection member and in the extracted area.
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