Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Reconfigurable hardware accelerator for boolean satisfiability solver










Image Number 7 for United States Patent #8131660.

A hardware accelerator is provided for Boolean constraint propagation (BCP) using field-programmable gate arrays (FPGAs) for use in solving the Boolean satisfiability problem (SAT). An inference engine may perform implications. Block RAM (BRAM) may be used to store SAT instance information. Computation may be co-located with the BRAM memory, taking advantage of the high on-chip bandwidth and low latency of an FPGA. SAT instances may be partitioned into multiple groups that can be processed by multiple inference engines in parallel. New SAT instances can be inserted into FPGA without invoking the time-consuming FPGA re-synthesizing process.








 
 
  Recently Added Patents
Preparation and use of meristematic cells belonging to the Dendrobium phalaenopsis, Ansellia, Polyrrhiza, Vanilla, Cattleya and Vanda genera with high content of phenylpropanoids, hydrosoluble
Maintenance guidance display device, maintenance guidance display method, and maintenance guidance display program
Semiconductor power amplifier
Tablet computer
Down-drawable, chemically strengthened glass for cover plate
Electronic flash device
Epilation apparatus
  Randomly Featured Patents
Portable baby bed
High-temperature protection layer
Method of making a cellular polymeric resin body in a self contained high-pressure mold form
Graphical user interface for a portion of a display screen
Method and apparatus for selectively marking a semiconductor wafer
Universal stethoscope amplifier with graphic equalization and teaching and learning ports
Redispersion of noble metals on supported catalysts
Power efficient instruction prefetch mechanism
LED spotlight
Method of changing a thermomagnetic tape duplicator to an anhysteretic type of tape duplicator