Resources Contact Us Home
Reconfigurable hardware accelerator for boolean satisfiability solver

Image Number 7 for United States Patent #8131660.

A hardware accelerator is provided for Boolean constraint propagation (BCP) using field-programmable gate arrays (FPGAs) for use in solving the Boolean satisfiability problem (SAT). An inference engine may perform implications. Block RAM (BRAM) may be used to store SAT instance information. Computation may be co-located with the BRAM memory, taking advantage of the high on-chip bandwidth and low latency of an FPGA. SAT instances may be partitioned into multiple groups that can be processed by multiple inference engines in parallel. New SAT instances can be inserted into FPGA without invoking the time-consuming FPGA re-synthesizing process.

  Recently Added Patents
Control apparatus for autonomous operating vehicle
Light powered hearing aid
Methods of forming semiconductor devices having diffusion regions of reduced width
Housekeeping cart
System for and method of providing single sign-on (SSO) capability in an application publishing environment
Mobile terminal based on W-CDMA system having receive diversity function and system thereof
Dual source mass spectrometry system
  Randomly Featured Patents
Failover communication services
Air core inductive element on printed circuit board for use in switching power conversion circuitries
Pulse width controlling logic circuit
Semiconductor structures including bodies of semiconductor material, devices including such structures and related methods
Canola oil with reduced linolenic acid
High resiliency network infrastructure
Neutron individual dose meter, neutron dose rate meter, neutron detector and its method of manufacture
Herbicidal and plant-growth-regulating 1,2,4-trisubstituted-1,2,4-triazolidin-3,5-dithiones
Image forming apparatus for forming an original image and an additional image
Underfloor junction box