Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Reconfigurable hardware accelerator for boolean satisfiability solver










Image Number 7 for United States Patent #8131660.

A hardware accelerator is provided for Boolean constraint propagation (BCP) using field-programmable gate arrays (FPGAs) for use in solving the Boolean satisfiability problem (SAT). An inference engine may perform implications. Block RAM (BRAM) may be used to store SAT instance information. Computation may be co-located with the BRAM memory, taking advantage of the high on-chip bandwidth and low latency of an FPGA. SAT instances may be partitioned into multiple groups that can be processed by multiple inference engines in parallel. New SAT instances can be inserted into FPGA without invoking the time-consuming FPGA re-synthesizing process.








 
 
  Recently Added Patents
Immunotherapy in cancer treatment
Portable electric circular saw
Tricyclic inhibitors of kinases
Optical module for a microlithography objective including holding and supporting devices
Method and apparatus for selective decoding in a wireless communication system
Measurement protocol for a medical technology apparatus
Navigation system and navigation apparatus
  Randomly Featured Patents
PC card and frame kit therefor
Demand modeling and prediction in a retail category
Protective device for a vehicle
Display stand
Arrangement for storing and launching payloads
Urethane resin compositions
Method for forming a DRAM capacitor using HSG-Si
Selective filtering of incoming telephone calls
Sunglasses including quick release lens retainer #5
Laminated wheel assembly