Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Reconfigurable hardware accelerator for boolean satisfiability solver










Image Number 7 for United States Patent #8131660.

A hardware accelerator is provided for Boolean constraint propagation (BCP) using field-programmable gate arrays (FPGAs) for use in solving the Boolean satisfiability problem (SAT). An inference engine may perform implications. Block RAM (BRAM) may be used to store SAT instance information. Computation may be co-located with the BRAM memory, taking advantage of the high on-chip bandwidth and low latency of an FPGA. SAT instances may be partitioned into multiple groups that can be processed by multiple inference engines in parallel. New SAT instances can be inserted into FPGA without invoking the time-consuming FPGA re-synthesizing process.








 
 
  Recently Added Patents
Method for media access controlling and system and method for channel time reservation in distributed wireless personal area network
Method and system for detecting data modification within computing device
System and method of verification of analog circuits
(4932
Method and system for parallelizing data copy in a distributed file system
Circuit arrangement and method for operating a circuit arrangement
Encoding and/or decoding memory devices and methods thereof
  Randomly Featured Patents
Process for dyeing keratinous fibers with aminoindoles and oxidation dye precursors at basic Ph's and dyeing agents
Method for determining .gamma.-glutamyltransferase activity and kits containing a novel substrate solution for use therein
Benzodiazepine derivatives
System and method for multi-site distributed object management environment
Piercing device for piercing ventilating holes in cigarettes or similar smoking commodities
Printer object list resolutions
Method for reading a wet fluorescent surface
Modified chip attach process and apparatus
System and method for interrupt distribution in a multithread processor
Fish lure