Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Reconfigurable hardware accelerator for boolean satisfiability solver










Image Number 7 for United States Patent #8131660.

A hardware accelerator is provided for Boolean constraint propagation (BCP) using field-programmable gate arrays (FPGAs) for use in solving the Boolean satisfiability problem (SAT). An inference engine may perform implications. Block RAM (BRAM) may be used to store SAT instance information. Computation may be co-located with the BRAM memory, taking advantage of the high on-chip bandwidth and low latency of an FPGA. SAT instances may be partitioned into multiple groups that can be processed by multiple inference engines in parallel. New SAT instances can be inserted into FPGA without invoking the time-consuming FPGA re-synthesizing process.








 
 
  Recently Added Patents
Uniform light source for an imaging instrument
3-D image night light gun
Convergent mediation system with dedicated online steams
Cartridge for storing biosample plates and use in automated data storage systems
Multi-touch sensing circuit
Local biomechanical and/or antimicrobial ligation device
Infant bodysuit
  Randomly Featured Patents
Method for forming micropattern of resist
Camera control apparatus, camera control method, and camera system
Indoor unit of an air conditioner system
Collapsible seat
Card payment method for service charge concerning to physical distribution or transportation
Deflectable medical therapy delivery device having common lumen profile
Anti-submarine vehicle occupant restraint system
Audio-visual navigation and communication dynamic memory architectures
Cyclical action massaging chair
Method for rapid imaging of thermographic materials by extending exposure time in a single beam laser scanner