Resources Contact Us Home
Reconfigurable hardware accelerator for boolean satisfiability solver

Image Number 7 for United States Patent #8131660.

A hardware accelerator is provided for Boolean constraint propagation (BCP) using field-programmable gate arrays (FPGAs) for use in solving the Boolean satisfiability problem (SAT). An inference engine may perform implications. Block RAM (BRAM) may be used to store SAT instance information. Computation may be co-located with the BRAM memory, taking advantage of the high on-chip bandwidth and low latency of an FPGA. SAT instances may be partitioned into multiple groups that can be processed by multiple inference engines in parallel. New SAT instances can be inserted into FPGA without invoking the time-consuming FPGA re-synthesizing process.

  Recently Added Patents
Case for camera
Correction information calculating device, image processing apparatus, image display system, and image correcting method
Valved, microwell cell-culture device and method
Portable massage apparatus
Semiconductor device and method of manufacturing the same
Display sheet, display device, and electronic apparatus
Device, information processing method, and computer-readable storage medium
  Randomly Featured Patents
Mortise lock
Adjustable shelf
Service pack variable displacement pump
System for generating electrical power
Solid compounds, self-sustaining combustion hydrogen generators containing borazane and/or polyaminoborane and at least one inorganic oxidant, and method for generating hydrogen
Peristaltic injector
Dispenser package set
Workpiece stocker with circular configuration
Dipmeter displacement processing technique
Washer backsplash assembly