Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Reconfigurable hardware accelerator for boolean satisfiability solver










Image Number 7 for United States Patent #8131660.

A hardware accelerator is provided for Boolean constraint propagation (BCP) using field-programmable gate arrays (FPGAs) for use in solving the Boolean satisfiability problem (SAT). An inference engine may perform implications. Block RAM (BRAM) may be used to store SAT instance information. Computation may be co-located with the BRAM memory, taking advantage of the high on-chip bandwidth and low latency of an FPGA. SAT instances may be partitioned into multiple groups that can be processed by multiple inference engines in parallel. New SAT instances can be inserted into FPGA without invoking the time-consuming FPGA re-synthesizing process.








 
 
  Recently Added Patents
Display control apparatus and display control method
Bed
Reference signal design for wireless communication system
Method for determining usage rate of breaking hammer, breaking hammer, and measuring device
Methods for treatment of migraine and symptoms thereof
Method and apparatus for estimating a downhole fluid property using a charged particle densitometer
Peptide biomarkers of cardiovascular disease
  Randomly Featured Patents
Cache memory usable as scratch pad storage
Apparatus and method for obtaining object-color component data
Ceiling fan
Pre-fetch control method
Preparing sterile articles from polymers containing a stabilizer based on a poly(oxyalkylene)
Retaining wall block system
Electrically activated RF switch accessory used with a portable radio
Optical instrument for measuring displacement
Rotary alternating piston machine with coupling lever rotating around offset crankpin
Designing memory for testability to support scan capability in an asic design