Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Reconfigurable hardware accelerator for boolean satisfiability solver










Image Number 7 for United States Patent #8131660.

A hardware accelerator is provided for Boolean constraint propagation (BCP) using field-programmable gate arrays (FPGAs) for use in solving the Boolean satisfiability problem (SAT). An inference engine may perform implications. Block RAM (BRAM) may be used to store SAT instance information. Computation may be co-located with the BRAM memory, taking advantage of the high on-chip bandwidth and low latency of an FPGA. SAT instances may be partitioned into multiple groups that can be processed by multiple inference engines in parallel. New SAT instances can be inserted into FPGA without invoking the time-consuming FPGA re-synthesizing process.








 
 
  Recently Added Patents
Systems and methods for detailed error reporting in data storage systems
Schottky diode and method of manufacture
Compound semiconductor device and manufacturing method therefor
Transmission apparatus and network protection method
Hybrid fin field-effect transistor structures and related methods
Managing device functionality during predetermined conditions
Power management systems and designs
  Randomly Featured Patents
Systems and methods for selective encryption of operating system metadata for host-based encryption of data at rest on a logical unit
Nuclear magnetic resonance diagnostic apparatus
Spotlight
Dry shaver
Floor duster
Recording method and apparatus
Knife with illuminated blade
Full track read for adaptive pre-fetching of data
Light emitting device and method for fabricating the same including a back surface electrode with an Au alloy
Injection molded in-line connector assembly for bipolar leads