Resources Contact Us Home
Reconfigurable hardware accelerator for boolean satisfiability solver

Image Number 7 for United States Patent #8131660.

A hardware accelerator is provided for Boolean constraint propagation (BCP) using field-programmable gate arrays (FPGAs) for use in solving the Boolean satisfiability problem (SAT). An inference engine may perform implications. Block RAM (BRAM) may be used to store SAT instance information. Computation may be co-located with the BRAM memory, taking advantage of the high on-chip bandwidth and low latency of an FPGA. SAT instances may be partitioned into multiple groups that can be processed by multiple inference engines in parallel. New SAT instances can be inserted into FPGA without invoking the time-consuming FPGA re-synthesizing process.

  Recently Added Patents
Controller interface providing improved data reliability
Image processing apparatus and image processing method
Method and apparatus for allocating erasure coded data to disk storage
Method and apparatus for allocating and obtaining IP address
Mobile communication method, mobile station, and network device
Multiplanar image displays and media formatted to provide 3D imagery without 3D glasses
Encryption using alternate authentication key
  Randomly Featured Patents
Embalming machine flow control apparatus
Method of checking the integrity of a source of additional memory for use in an electronically controlled sewing machine
Winch handle
Aircraft brake heat shield having easily removed heat shield sections
Amplifying solid-state imaging device, and method for driving the same
Diversional and therapeutic device for organic brain syndrome patients
Drive device of variable transmission ratio, particularly for operating an internal combustion engine supercharger
Tread pattern having at least one inserted element
Pneumatic fiber recovery and redistribution system for sliver high pile fabric knitting machines
Low intensity X-ray and gamma-ray imaging device