Resources Contact Us Home
Reconfigurable hardware accelerator for boolean satisfiability solver

Image Number 3 for United States Patent #8131660.

A hardware accelerator is provided for Boolean constraint propagation (BCP) using field-programmable gate arrays (FPGAs) for use in solving the Boolean satisfiability problem (SAT). An inference engine may perform implications. Block RAM (BRAM) may be used to store SAT instance information. Computation may be co-located with the BRAM memory, taking advantage of the high on-chip bandwidth and low latency of an FPGA. SAT instances may be partitioned into multiple groups that can be processed by multiple inference engines in parallel. New SAT instances can be inserted into FPGA without invoking the time-consuming FPGA re-synthesizing process.

  Recently Added Patents
Systems and methods for facilitating communication with foundation fieldbus linking devices
Adjustable box extender
High conductive water-based silver ink
Wild card auto completion
Adjustable voltage regulator with dynamic voltage compensation
Stabilised prostaglandin composition
Adhering composition and method of applying the same
  Randomly Featured Patents
Liquid crystal display device
Solenoid valve for brake systems
Frequency doubling a Q-switched laser beam by using intracavity Type II phase matching
Kit to form a wood splitting apparatus
Apparatus for bevelling wafer-edge
Image forming apparatus having a process cartridge for receiving power from a power supplying member
Image processing device, image processing method, and recording method for managing log of output image data
Correction tape dispenser
Peach tree named `Flordabest`
Laying out web components using mounting and pooling functions