Resources Contact Us Home
Reconfigurable hardware accelerator for boolean satisfiability solver

Image Number 3 for United States Patent #8131660.

A hardware accelerator is provided for Boolean constraint propagation (BCP) using field-programmable gate arrays (FPGAs) for use in solving the Boolean satisfiability problem (SAT). An inference engine may perform implications. Block RAM (BRAM) may be used to store SAT instance information. Computation may be co-located with the BRAM memory, taking advantage of the high on-chip bandwidth and low latency of an FPGA. SAT instances may be partitioned into multiple groups that can be processed by multiple inference engines in parallel. New SAT instances can be inserted into FPGA without invoking the time-consuming FPGA re-synthesizing process.

  Recently Added Patents
Dynamic lookup service in a distributed system
Method for inhibiting thermal run-away
Vehicles with electric motor
Combined high and low frequency stimulation therapy
Method and apparatus of motion vector prediction with extended motion vector predictor
Transaction finance processing system and approach
Picture quality control method and image display using same
  Randomly Featured Patents
Alkaline ophthalmic suspensions
Amorphous solar module having improved passivation
Fluorescence energy transfer by competitive hybridization
Method of making a semiconductor integrated circuit device utilizing simultaneous outdiffusion and autodoping during epitaxial deposition
Process for displaying measuring results in graphic form in test apparatus for testing textile goods and apparatus for carrying out the process
Motor-driven, expander-compressor transducer
Digital signal processor/known good die packaging using rerouted existing package for test and burn-in carriers
Aerodynamic wheel cover
Optical system in the ray path of a confocal fluorescence microscope