Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Reconfigurable hardware accelerator for boolean satisfiability solver










Image Number 3 for United States Patent #8131660.

A hardware accelerator is provided for Boolean constraint propagation (BCP) using field-programmable gate arrays (FPGAs) for use in solving the Boolean satisfiability problem (SAT). An inference engine may perform implications. Block RAM (BRAM) may be used to store SAT instance information. Computation may be co-located with the BRAM memory, taking advantage of the high on-chip bandwidth and low latency of an FPGA. SAT instances may be partitioned into multiple groups that can be processed by multiple inference engines in parallel. New SAT instances can be inserted into FPGA without invoking the time-consuming FPGA re-synthesizing process.








 
 
  Recently Added Patents
Mixture, especially spinning solution
Package for product
Image enhancement based on multiple frames and motion estimation
External preparation composition for skin comprising ginseng flower or ginseng seed extracts
Edge alphas for image translation
Biaxially oriented film which could be thermally laminated with paper and other substrates
Imaging device and imaging method
  Randomly Featured Patents
Electronic medication chronolog device
Polymerizable compositions in non-flowable forms
Method of mass producing printed circuit antennas
Process for ethylbenzene production
Spray skirt with rigid deck
Plants and seeds of corn variety I226276
System and method for remote monitoring of RF units in base station of wireless communication network
Hologram imaging device and method of using same
Methods and apparatuses for file synchronization and updating using a signature list
Power-driven golf cup cutter