Resources Contact Us Home
Reconfigurable hardware accelerator for boolean satisfiability solver

Image Number 3 for United States Patent #8131660.

A hardware accelerator is provided for Boolean constraint propagation (BCP) using field-programmable gate arrays (FPGAs) for use in solving the Boolean satisfiability problem (SAT). An inference engine may perform implications. Block RAM (BRAM) may be used to store SAT instance information. Computation may be co-located with the BRAM memory, taking advantage of the high on-chip bandwidth and low latency of an FPGA. SAT instances may be partitioned into multiple groups that can be processed by multiple inference engines in parallel. New SAT instances can be inserted into FPGA without invoking the time-consuming FPGA re-synthesizing process.

  Recently Added Patents
System for and method of providing single sign-on (SSO) capability in an application publishing environment
Imaging device, method and computer readable medium
Multi charged particle beam writing apparatus and multi charged particle beam writing method
Terminal for flat test probe
Integrated multi-sat LNB and frequency translation module
Laboratory spatula
Wafer level packaging structure with large contact area and preparation method thereof
  Randomly Featured Patents
Use of naphtha as riser diluent in carbo-metallic oil conversion
Microwave linear oscillator/amplifier utilizing a multicoupled ferrite resonator
Lock with sensor
Persistent data storage techniques
Curable organopolysiloxane compositions with improved adhesion
Liquid crystal polyester resin composition
Torque transmitting device with backlas-compensation
Paperboard shipping chock and assembly
Security sliding door system