Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Reconfigurable hardware accelerator for boolean satisfiability solver










Image Number 3 for United States Patent #8131660.

A hardware accelerator is provided for Boolean constraint propagation (BCP) using field-programmable gate arrays (FPGAs) for use in solving the Boolean satisfiability problem (SAT). An inference engine may perform implications. Block RAM (BRAM) may be used to store SAT instance information. Computation may be co-located with the BRAM memory, taking advantage of the high on-chip bandwidth and low latency of an FPGA. SAT instances may be partitioned into multiple groups that can be processed by multiple inference engines in parallel. New SAT instances can be inserted into FPGA without invoking the time-consuming FPGA re-synthesizing process.








 
 
  Recently Added Patents
State detection device, electronic apparatus, measurement system and program
Virtual image display device and manufacturing method of virtual image display device
Nonvolatile semiconductor memory device and method of manufacturing the same
Method and structure of forming backside through silicon via connections
Determination method for a reinitialization of a temporal sequence of fluoroscopic images of an examination region of an examination object
Associating objects in databases by rate-based tagging
Quantum dot template for fast and simultaneous detection of different infectious agents
  Randomly Featured Patents
Fabrication of through-silicon vias on silicon wafers
Paint adjustment ring for a spray gun
Engine induction system having a telescopic throttle body
Rotor assembly
Organic electroluminescent lighting device
Compact system unit for personal computers
Cleaning card for time recorder
Initiator activated by a stimulus
Optical signal processing modules
Class AB output amplifier stage