Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Reconfigurable hardware accelerator for boolean satisfiability solver










Image Number 3 for United States Patent #8131660.

A hardware accelerator is provided for Boolean constraint propagation (BCP) using field-programmable gate arrays (FPGAs) for use in solving the Boolean satisfiability problem (SAT). An inference engine may perform implications. Block RAM (BRAM) may be used to store SAT instance information. Computation may be co-located with the BRAM memory, taking advantage of the high on-chip bandwidth and low latency of an FPGA. SAT instances may be partitioned into multiple groups that can be processed by multiple inference engines in parallel. New SAT instances can be inserted into FPGA without invoking the time-consuming FPGA re-synthesizing process.








 
 
  Recently Added Patents
Method and apparatus for executing load distributed printing
Chemically bonded carbon nanotube-polymer hybrid and nanocomposite thereof
Location-type tagging using collected traveler data
Autobrake and decel control built-in test equipment
Power generating apparatus of renewable energy type and method of attaching and detaching blade
Method for production of a thermoelectric apparatus
Isolation rings for blocking the interface between package components and the respective molding compound
  Randomly Featured Patents
High intensity arc lamp
Cross
Image forming apparatus, image forming method, and image forming program product for processing pixels of vertical and diagonal lines expressed by input multi-value pixel data
Logic for generating multicast/unicast address (es)
Processor for forms with multi-format data
Automatic retractable safety penetrating instrument
Snowboard boot and binding apparatus
Photothermographic element comprising particles each containing silver halide, a silver compound and reducing agent
Lamp base
Bow calibrating device