Resources Contact Us Home
Reconfigurable hardware accelerator for boolean satisfiability solver

Image Number 3 for United States Patent #8131660.

A hardware accelerator is provided for Boolean constraint propagation (BCP) using field-programmable gate arrays (FPGAs) for use in solving the Boolean satisfiability problem (SAT). An inference engine may perform implications. Block RAM (BRAM) may be used to store SAT instance information. Computation may be co-located with the BRAM memory, taking advantage of the high on-chip bandwidth and low latency of an FPGA. SAT instances may be partitioned into multiple groups that can be processed by multiple inference engines in parallel. New SAT instances can be inserted into FPGA without invoking the time-consuming FPGA re-synthesizing process.

  Recently Added Patents
Human embryonic stem cell methods and PODXL expression
Highly stable electrolytic water with reduced NMR half line width
Quinoline compounds and their use for treating viral infection
Method for execution upon processing of at least one histological sample
System and method for detecting deadlock in a multithread program
Multilayered ceramic electronic component and fabrication method thereof
Cognitive radio cooperative spectrum sensing method and fusion center performing cognitive radio cooperative spectrum sensing
  Randomly Featured Patents
Zoom lens system
Magnetic resonance imaging using blood flow navigation
Ski boot
1-(3,3-Diaryl-3-oxadiazolalkyl)-4-phenyl-4-piperidinomethanols and related compounds
System for producing a colored motion picture film from black-and-white medium
Method and device for catheterization
EML transmitter applying band stop filter
Method and apparatus for controlling wafer uniformity using spatially resolved sensors
Bubble forming and projecting device
Ink remainder detecting module for ink jet apparatus, ink container with same and ink jet apparatus