Resources Contact Us Home
Reconfigurable hardware accelerator for boolean satisfiability solver

Image Number 3 for United States Patent #8131660.

A hardware accelerator is provided for Boolean constraint propagation (BCP) using field-programmable gate arrays (FPGAs) for use in solving the Boolean satisfiability problem (SAT). An inference engine may perform implications. Block RAM (BRAM) may be used to store SAT instance information. Computation may be co-located with the BRAM memory, taking advantage of the high on-chip bandwidth and low latency of an FPGA. SAT instances may be partitioned into multiple groups that can be processed by multiple inference engines in parallel. New SAT instances can be inserted into FPGA without invoking the time-consuming FPGA re-synthesizing process.

  Recently Added Patents
Adsorptive molded parts and the use thereof
Method for preventing wheat from mycotoxin contamination
Bioelectric battery for implantable device applications
Integrated circuit packaging system with interconnects and method of manufacture thereof
Embedded package and method for manufacturing the same
Optoelectronic devices and a method for producing the same
Mixed reactant flow-by fuel cell
  Randomly Featured Patents
Semiconductor device and method for driving the same
Protective frame structure at rear of vehicle
Drinking container cap
Integrated circuit card with fingerprint verification capability
Electrochemical device and methods for producing the same
Aligning optical components of an optical measuring system
Key storage device
Phenothiazine cytokine inhibitors
Composite single pane window for an aircraft and method of making same
Air cargo centerline restraint system having restraints mounted over floor joists outside the wingbox area for lateral support