Resources Contact Us Home
Semiconductor memory device

Image Number 4 for United States Patent #8130581.

The present invention provides a semiconductor memory device in which the number of write amplifiers is decreased by increasing the number of bit line pairs connected to one pair of common write data lines. Further, by decreasing the number of bit line pairs connected to one pair of common read data lines, parasitic capacitance connected to the pair of common read data lines is reduced and, accordingly, time in which the potential difference between the pair of common read data lines increases is shortened. Thus, while preventing enlargement of the chip layout area, read time can be shortened.

  Recently Added Patents
Method and apparatus for prioritizing data transfer
Systems and method for automatic color plane misregistration calibration
Water slide
Apparatus and method for scrolling a screen of a portable terminal having a touch screen
Computer systems and methods for the query and visualization of multidimensional databases
Method and an apparatus for processing an audio signal
Circuits for prevention of reverse leakage in charge pumps
  Randomly Featured Patents
Molecules containing at least one peptide sequence carrying one or several epitopes characteristic of a protein produced by P. falciparum at the sporozoite stage and in the hepatocytes
In line gun support arrangement with expansion compensation
Floating magnetic head
Modular EDM system
Geophysical and geochemical exploration
Expansion valve with inlet strainer
Secure software distribution and installation
Conveyor belt
Sampling apparatus for collecting samples from underwater hydrothermal vents and the marine or limnological water column
Hanger unit for cable or similar articles