Resources Contact Us Home
Semiconductor memory device

Image Number 4 for United States Patent #8130581.

The present invention provides a semiconductor memory device in which the number of write amplifiers is decreased by increasing the number of bit line pairs connected to one pair of common write data lines. Further, by decreasing the number of bit line pairs connected to one pair of common read data lines, parasitic capacitance connected to the pair of common read data lines is reduced and, accordingly, time in which the potential difference between the pair of common read data lines increases is shortened. Thus, while preventing enlargement of the chip layout area, read time can be shortened.

  Recently Added Patents
Second order correction circuit and method for bandgap voltage reference
Messenger bag
Display screen or portion thereof with graphical user interface
Patterned MR device with controlled shape anisotropy
Apparatus for counting particles in a gas
Electrical converter with variable capacitor
Hand-held optical probe based imaging system with 3D tracking facilities
  Randomly Featured Patents
Process for fabricating compliant layer board with selectively isolated solder pads
Automatic transmission shifter assembly for automotive vehicles
Tool for fertilizing plants, trees and shrubs
Image forming apparatus and method for changeable image forming modes between a single color mode and a multiple color mode
Modular compartmentalized conveyor belt system
Infeed assembly for random length end shaping machine
Thermal reclamation method
Processor and method for recovering global history shift register and return address stack thereof by determining a removal range of a branch recovery table
Data input buffer
Pen cap