Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Write circuitry for hierarchical memory architecture










Image Number 4 for United States Patent #8130567.

A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry.








 
 
  Recently Added Patents
Method for building taxonomy of topics and categorizing videos
(4926
Systems and methods for excluding undesirable network transactions
Dual-leadframe multi-chip package and method of manufacture
Visibility radio cap and network
Real-image zoom viewfinder and imaging apparatus
Methods and systems for sending messages regarding an emergency that occurred at a facility
  Randomly Featured Patents
Method of forming pattern having optical angle in charged particle exposure system
Internally shock caged serpentine flexure for micro-machined accelerometer
Cooling system for electronic assembly
System and method relating to packet data communication
Gage bar for miter cutting machine
Semiconductor memory device having refresh size setting circuit
Health pillow
Method of fixing a cathode-ray tube cone and display window prior to sealing and a cathode-ray tube manfactured by such a method
Packaging structure and method for OLED
Vehicle theft deterrent apparatus and method