Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Write circuitry for hierarchical memory architecture










Image Number 4 for United States Patent #8130567.

A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry.








 
 
  Recently Added Patents
Recording medium, playback device, integrated circuit
Method of forming micropattern, method of forming damascene metallization, and semiconductor device and semiconductor memory device fabricated using the same
Communication terminal device, communication system, and communication control method
Fluid pressure responsive electric switch
Sample analyzing device
Beverage container lid
Micro-fluidic device
  Randomly Featured Patents
Flexible high speed micro-cable
Active organic semiconductor devices and methods for making the same
Preparation of polycarbynes and diamond-like carbon materials made therefrom
System for resolving memory access conflicts among processors and minimizing processor waiting times for access to memory by comparing waiting times and breaking ties by an arbitrary priority
Connection device for a fluid duct
Magnetic bubble multilayer arrangement
Method for effectively transmitting control signal in wireless communication system
Semiconductor device and manufacturing method thereof
Ladder gate LDDFET
Two-package curing type polyurethane coating composition and coated article