Resources Contact Us Home
Write circuitry for hierarchical memory architecture

Image Number 4 for United States Patent #8130567.

A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry.

  Recently Added Patents
Multi-chip package with a supporting member and method of manufacturing the same
Preventative traffic congestion social networking improvement system within a community
Cantilevered probe detector with piezoelectric element
Liquid low temperature injection molding process
Automatic detection of image degradation in enhanced vision systems
Tranverse in-core probe monitoring and calibration device for nuclear power plants, and method thereof
System for the secure management of digitally controlled locks, operating by means of crypto acoustic credentials
  Randomly Featured Patents
Balanced optical system
Heat-assisted magnetic recording head with laser diode
Lever switch and method of operating the same
Surface-coated cemented carbide article and a process for the production thereof
Sprayable lightweight ablative coating
Immittance monitoring apparatus
Eyebrow embroidery machine
Bed frame
Electrophotographic recording apparatus
Bottom lead semiconductor package with recessed leads and fabrication method thereof