Resources Contact Us Home
Write circuitry for hierarchical memory architecture

Image Number 4 for United States Patent #8130567.

A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry.

  Recently Added Patents
Vehicle hood
Apparatus, electronic component and method for generating reference voltage
Method and system for video parameter analysis and transmission
Radiation detector array
Communication system and data transmission method thereof
Method and system for delivering and executing virtual container on logical partition of target computing device
Semiconductor memory device
  Randomly Featured Patents
Fan assembly for vehicles
Paperboard container reinforcing method
Mobile radio communication system
Bidirectional video telephony between cable television and switched telephone systems
Chrysanthemum plant named Pacific Isle
Method of forming an optical compensating plate of a liquid crystal display apparatus
Thioamide compounds, method of making and method of using thereof
Handover method, base station, mobile station, and mobile communication system
Electronic target game apparatus and method
Method for providing load diffusion in data stream correlations