Image Number 14 for United States Patent #8130559.
In one aspect, a multiplexer array is described. The multiplexer array includes (1) a first multiplexer coupled to a first address line, where the first multiplexer includes a first plurality of memory devices and (2) a first plurality of input logic devices coupled to the first multiplexer, a first plurality of data lines, and a plurality of bitlines. Each input logic device of the first plurality of input logic devices is coupled to a respective memory device of the first plurality of memory devices and includes a first input terminal and a second input terminal, where, for each input logic device, the first input terminal is coupled to a respective data line of the first plurality of data lines and the second input terminal is coupled to a respective bitline of the plurality of bitlines. Embodiments of methods of programming a multiplexer array are also described.