Resources Contact Us Home
Pair bit line programming to improve boost voltage clamping

Image Number 19 for United States Patent #8130556.

A programming technique reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an inhibited channel to avoid program disturb. One aspect groups alternate pairs of adjacent bit lines into first and second sets. Dual programming pulses are applied to a selected word line. The first set of bit lines is programmed during the first pulse, and the second set of bit lines is programmed during the second pulse. A verify operation is then performed for all bit lines. When a particular bit line is inhibited, at least one of its neighbor bit lines will also be inhibited so that the channel of the particular bit line will be sufficiently boosted. Another aspect programs every third bit line separately. A modified layout allows adjacent pairs of bit lines to be sensed using odd-even sensing circuitry.

  Recently Added Patents
Tab visibility
Porous polymeric resins
Generating and using checkpoints in a virtual computer system
Modular sport center
Data latch circuit and electronic device
Transmission device
Maltol ether processes and intermediates
  Randomly Featured Patents
Heterocyclic anti-viral compounds comprising metabolizable moieties and their uses
Method and system for wafer level testing and burning-in semiconductor components
Joint for connecting sprinklers to underground water pipes
Stoppers for individual beverage containers
Method and apparatus to manage packet fragmentation
Rare earth magnet
Multi-layer high energy propellants
Limitation of oscillation caused by Raman amplification due to the use of different fibers
Vehicle safety device actuating circuit with monitoring current regulator
Acoustic wave device, and filter and duplexer using the same