Resources Contact Us Home
Pair bit line programming to improve boost voltage clamping

Image Number 19 for United States Patent #8130556.

A programming technique reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an inhibited channel to avoid program disturb. One aspect groups alternate pairs of adjacent bit lines into first and second sets. Dual programming pulses are applied to a selected word line. The first set of bit lines is programmed during the first pulse, and the second set of bit lines is programmed during the second pulse. A verify operation is then performed for all bit lines. When a particular bit line is inhibited, at least one of its neighbor bit lines will also be inhibited so that the channel of the particular bit line will be sufficiently boosted. Another aspect programs every third bit line separately. A modified layout allows adjacent pairs of bit lines to be sensed using odd-even sensing circuitry.

  Recently Added Patents
Image playback device and method and electronic camera with image playback function
Data processing circuit with arbitration between a plurality of queues
Method for delivering a volatile material
Packaging article
Fixing apparatus
Liquid-filled protein-phosphatidic acid capsule dispersions
Semiconductor IC including pulse generation logic circuit
  Randomly Featured Patents
Method of distributing program to a plurality of nodes within a network by using gateway
System, method and computer program product for generating software cards that summarize and index information
Oscillator gain circuit and method
Single-ended optical logic arrangement
Shaft rod for weaving machines
Multiphase epoxy thermosets having rubber within disperse phase
Thermostable glazing
Process for preparing vinyl chloride resin-acrylic graft copolymer composition
High expansion two-component structural foam
OPC based illumination optimization with mask error constraints