Resources Contact Us Home
Pair bit line programming to improve boost voltage clamping

Image Number 19 for United States Patent #8130556.

A programming technique reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an inhibited channel to avoid program disturb. One aspect groups alternate pairs of adjacent bit lines into first and second sets. Dual programming pulses are applied to a selected word line. The first set of bit lines is programmed during the first pulse, and the second set of bit lines is programmed during the second pulse. A verify operation is then performed for all bit lines. When a particular bit line is inhibited, at least one of its neighbor bit lines will also be inhibited so that the channel of the particular bit line will be sufficiently boosted. Another aspect programs every third bit line separately. A modified layout allows adjacent pairs of bit lines to be sensed using odd-even sensing circuitry.

  Recently Added Patents
Bull stationery tab
Engineered nucleic acids encoding a modified erythropoietin and their expression
Weak acid recovery system for ethanol separation processes
Reconfigurable barrel shifter and rotator
Arbitration circuit to arbitrate conflict between read/write command and scan command and display driver integrated circuit having the same
Externally gapped line arrester
Method for transmitting a signal
  Randomly Featured Patents
Electrical connector
Optical axis orientation measuring device, optical axis orientation measuring method, spherical surface wave device manufacturing device, and spherical surface wave device manufacturing method
Hydrophilic polyurethane composition
Dynamic retrieval of routing information for inter-AS TE-LSPs
Cyclodextrin-based polymers for therapeutics delivery
Audio message system with programmer
Pressure release parking brake actuator
Silanes useful as anti-treeing additives
Voting in chat system without topic-specific rooms