Resources Contact Us Home
Pair bit line programming to improve boost voltage clamping

Image Number 19 for United States Patent #8130556.

A programming technique reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an inhibited channel to avoid program disturb. One aspect groups alternate pairs of adjacent bit lines into first and second sets. Dual programming pulses are applied to a selected word line. The first set of bit lines is programmed during the first pulse, and the second set of bit lines is programmed during the second pulse. A verify operation is then performed for all bit lines. When a particular bit line is inhibited, at least one of its neighbor bit lines will also be inhibited so that the channel of the particular bit line will be sufficiently boosted. Another aspect programs every third bit line separately. A modified layout allows adjacent pairs of bit lines to be sensed using odd-even sensing circuitry.

  Recently Added Patents
Method and system for filtering noises in an image scanned by charged particles
Modulation of TIM receptor activity in combination with cytoreductive therapy
Method of preparing enteric hard capsule and enteric hard capsule prepared thereby
Information processing using batch setting information
Heterocyclic compounds as CCR2B antagonists
Pyridazine compounds for controlling invertebrate pests
  Randomly Featured Patents
Air cleaner
Memory-based error recovery
GPS based search and rescue system
Method for producing polyetherpolyols in the presence of a multi-metal cyanide complex catalyst
Automated voice pattern filter
Injection molded case for optical storage discs
Thermoplastic resin composition
Container convertible into air cushion support
Transducer shield
Rear axle arrangement for a heavy vehicle