Resources Contact Us Home
Pair bit line programming to improve boost voltage clamping

Image Number 19 for United States Patent #8130556.

A programming technique reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an inhibited channel to avoid program disturb. One aspect groups alternate pairs of adjacent bit lines into first and second sets. Dual programming pulses are applied to a selected word line. The first set of bit lines is programmed during the first pulse, and the second set of bit lines is programmed during the second pulse. A verify operation is then performed for all bit lines. When a particular bit line is inhibited, at least one of its neighbor bit lines will also be inhibited so that the channel of the particular bit line will be sufficiently boosted. Another aspect programs every third bit line separately. A modified layout allows adjacent pairs of bit lines to be sensed using odd-even sensing circuitry.

  Recently Added Patents
Semiconductor device
Context-sensitive views
Vehicle having power supply apparatus
Memory device and self interleaving method thereof
String changing tool with a quick connector assembly and worm gear string cutter
Radio communication system, base station apparatus, terminal apparatus, and radio communication method for radio communication system
  Randomly Featured Patents
Electric power steering apparatus
System for displaying images
Method of inhibiting cell proliferation using an anti-oncogene protein
Image sensor and image forming apparatus
Doppler radar flowmeter
Method and apparatus for calculating a focus metric
Power transfer of piezoelectric generated energy
Microwave plasma CVD of NANO structured tin/carbon composites
Bowling alley lane guard
Chair back adjustment mechanism