Resources Contact Us Home
Pair bit line programming to improve boost voltage clamping

Image Number 19 for United States Patent #8130556.

A programming technique reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an inhibited channel to avoid program disturb. One aspect groups alternate pairs of adjacent bit lines into first and second sets. Dual programming pulses are applied to a selected word line. The first set of bit lines is programmed during the first pulse, and the second set of bit lines is programmed during the second pulse. A verify operation is then performed for all bit lines. When a particular bit line is inhibited, at least one of its neighbor bit lines will also be inhibited so that the channel of the particular bit line will be sufficiently boosted. Another aspect programs every third bit line separately. A modified layout allows adjacent pairs of bit lines to be sensed using odd-even sensing circuitry.

  Recently Added Patents
Method and apparatus for wireless transmission of diagnostic information
Process for brominating unsaturated organic compounds with removal of quaternary ammonium or quaternary phosphonium monochlorides
Distylium plant named `PIIDIST-I`
Solid state lighting circuit and controls
Evaluation compiler method
Method and assembly for determining the temperature of a test sensor
Organic light emitting display apparatus
  Randomly Featured Patents
Process and device for the continuous casting of very small-diameter wires directly from liquid metal
Method for pre-shaping a semiconductor substrate for polishing and structure
Arrangement for cooling fluids
Couples for terminating optical fiber ends
Anesthetic gas exhaust system
Verification of soft error resilience
Method and apparatus for controlling transformation of two and three-dimensional images
Back rest for use in resting against a tree
Sanitary napkin
Expression of enzymatically active reverse transcriptase