Resources Contact Us Home
Pair bit line programming to improve boost voltage clamping

Image Number 19 for United States Patent #8130556.

A programming technique reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an inhibited channel to avoid program disturb. One aspect groups alternate pairs of adjacent bit lines into first and second sets. Dual programming pulses are applied to a selected word line. The first set of bit lines is programmed during the first pulse, and the second set of bit lines is programmed during the second pulse. A verify operation is then performed for all bit lines. When a particular bit line is inhibited, at least one of its neighbor bit lines will also be inhibited so that the channel of the particular bit line will be sufficiently boosted. Another aspect programs every third bit line separately. A modified layout allows adjacent pairs of bit lines to be sensed using odd-even sensing circuitry.

  Recently Added Patents
Coding circuitry for difference-based data transformation
Process and apparatus for producing composite material that includes carbon nanotubes
Managing breakpoints in a multi-threaded environment
Light-emitting device with a spacer at bottom surface
Television with a stand
Drive coil, measurement probe comprising the drive coil and methods utilizing the measurement probe
Antagonists of the glucagon receptor
  Randomly Featured Patents
Reusable endoscopic surgical instrument
Method and apparatus for interactive audience participation at a live entertainment event
Movement activated odor control animal litter
Fuel delivery system using two pressure regulators with a single electric fuel pump
Dust control loading device
Rehabilitation and exercise apparatus
Metal artifact correction in computed tomography
Zoom lens
Device for data acquisition
Heterocyclic compounds