Resources Contact Us Home
Pair bit line programming to improve boost voltage clamping

Image Number 19 for United States Patent #8130556.

A programming technique reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an inhibited channel to avoid program disturb. One aspect groups alternate pairs of adjacent bit lines into first and second sets. Dual programming pulses are applied to a selected word line. The first set of bit lines is programmed during the first pulse, and the second set of bit lines is programmed during the second pulse. A verify operation is then performed for all bit lines. When a particular bit line is inhibited, at least one of its neighbor bit lines will also be inhibited so that the channel of the particular bit line will be sufficiently boosted. Another aspect programs every third bit line separately. A modified layout allows adjacent pairs of bit lines to be sensed using odd-even sensing circuitry.

  Recently Added Patents
Device and method for superimposing patterns on images in real time, particularly for guidance by location
Synthesized interoperable communications
Rose plant named `Esm R068`
Web development environment that enables a developer to interact with run-time output presentation of a page
System and method for combining different tablets into a pouch
Method for manufacturing non-volatile memory device, non-volatile memory element, and non-volatile memory device
Wire guide
  Randomly Featured Patents
Super radiant light source
Linear induction motor
Single-electron transistors and fabrication methods in which a projecting feature defines spacing between electrodes
Food stirrer
Phosphate-free dishwasher detergent with excellent rinsing power
Collision avoidance/proximity warning system using secondary radar
Package for stain treatment device
Bushing construction for precision-fit pivot assemblies
Linear light emitting apparatus
Beer brewing stand