Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Pair bit line programming to improve boost voltage clamping










Image Number 19 for United States Patent #8130556.

A programming technique reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an inhibited channel to avoid program disturb. One aspect groups alternate pairs of adjacent bit lines into first and second sets. Dual programming pulses are applied to a selected word line. The first set of bit lines is programmed during the first pulse, and the second set of bit lines is programmed during the second pulse. A verify operation is then performed for all bit lines. When a particular bit line is inhibited, at least one of its neighbor bit lines will also be inhibited so that the channel of the particular bit line will be sufficiently boosted. Another aspect programs every third bit line separately. A modified layout allows adjacent pairs of bit lines to be sensed using odd-even sensing circuitry.








 
 
  Recently Added Patents
Bottle
Transmitting apparatus and retransmitting method
Additives for oil recovery from reservoirs
Sink
Image playback device and method and electronic camera with image playback function
Elegant solutions for fingerprint image enhancement
Device for preparing a body fluid for a bacteriological analysis
  Randomly Featured Patents
Selectively coupling to feed points of an antenna system
Multiprotocol label switching routers
Soft contact lens with contamination indicator
Tire pressure monitoring system
Combined trackball and mouse
Method of and arrangements for coding and decoding color television signals using a separate series arrangement of a low-pass filter and a vertical temporal filter for each color difference si
Bladder type fluid accumulator for hydraulic system
Microbellows actuator
Sealing board and method for producing the same
Invertible prefabricated door