Image Number 11 for United States Patent #8129799.
A field-effect transistor (142) includes a lowly p-doped region 110 formed on a surface of a substrate (102), an n-doped drain region 112 and n-doped source region 114 arranged on a surface of the lowly p-doped region 110, and a device isolation insulating film 132 and device isolation insulating film 134. Here, the device isolation insulating film 132 is formed greater in film thickness than the device isolation insulating film 134; and in the n-doped source region 114, the peak concentration section having a highest dopant concentration is formed in a deeper position than in the n-doped drain region 112.
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