Resources Contact Us Home
EEPROM with increased reading speed

Image Number 12 for United States Patent #8129774.

In an EEPROM consisting of a NAND cell in which a plurality of memory cells are connected in series, the control gate voltage of the memory cell in a block selected by the data read operation is made different from the each of the voltages V.sub.sg1, V.sub.sg2 of the select gate of the select transistor in the selected block so as to make it possible to achieve a high speed reading without bringing about the breakdown of the insulating film interposed between the select gate and the channel of the select transistor. The high speed reading can also be made possible in the DINOR cell, the AND cell, NOR cell and the NAND cell having a single memory cell connected thereto, if the control gate voltage of the memory cell is made different from the voltage of the select gate of the select transistor.

  Recently Added Patents
Classification of a signal in a time domain
Spring-less buried magnet linear-resonant motor
Photocurable composition and process for producing molded product having fine pattern on its surface
Data storage device with power-off recovery system and method thereof
Communications system for a helmet
Protocols for high performance computing visualization, computational steering and forward progress
  Randomly Featured Patents
Amorphous nylon composition and films
Door hinge for motor vehicle
Apparatus and method for forming a tube article on a core
Refactoring virtual data storage hierarchies
Method of manufacturing a semiconductor device including a silicide layer having an NiSi phase provided on source and drain regions
Protecting a data processing system from attack by a vandal who uses a vulnerability scanner
System and method for replacing binary level masks in a page description
Apparatus and method for the processing, particularly the decontamination, of materials
Electrical connector with signal compensation
Cassette mounting on door of recording apparatus