Resources Contact Us Home
Method for creating tensile strain by applying stress memorization techniques at close proximity to the gate electrode

Image Number 5 for United States Patent #8129236.

After forming the outer drain and source regions of an N-channel transistor, the spacer structure may be removed on the basis of an appropriately designed etch stop layer so that a rigid material layer may be positioned more closely to the gate electrode, thereby enhancing the overall strain-inducing mechanism during a subsequent anneal process in the presence of the material layer and providing an enhanced stress memorization technique (SMT). In some illustrative embodiments, a selective SMT approach may be provided.

  Recently Added Patents
Substituted phenylsulfur trifluoride and other like fluorinating agents
Catalyst compositions for hydroformylation reaction and hydroformylation process using the same
Molten alloy solidification analyzing method and solidification analyzing program for performing the same
Hydrogen generation device and fuel cell system
Gas flow indicator
Catalyst composition with nanometer crystallites for slurry hydrocracking
Support tray for server
  Randomly Featured Patents
Storage device and data transfer method for the same
Method of synchronizing an internal-combustion engine without a cam position sensor
Electrical connector with improved electrostatic discharge system
Plastic film
X-ray imaging apparatus and X-ray imaging method
Method and apparatus for converting a faucet to a hand-held shower
Method of coating semiconductor wafer with resin and mold used therefor
Parallel wrapped tube heat exchanger
Water immersion alarm system
Miswiring circuit coupled to an electrical fault interrupter