Resources Contact Us Home
Method for creating tensile strain by applying stress memorization techniques at close proximity to the gate electrode

Image Number 5 for United States Patent #8129236.

After forming the outer drain and source regions of an N-channel transistor, the spacer structure may be removed on the basis of an appropriately designed etch stop layer so that a rigid material layer may be positioned more closely to the gate electrode, thereby enhancing the overall strain-inducing mechanism during a subsequent anneal process in the presence of the material layer and providing an enhanced stress memorization technique (SMT). In some illustrative embodiments, a selective SMT approach may be provided.

  Recently Added Patents
Emergency power-off button with proximity alarm
Sensing device and electronic apparatus
Signal processing apparatus, display apparatus having the same, and signal processing method
Quantitative sleep analysis system and method
Method and apparatus for detecting and tracking vehicles
Variety corn line KDC7040
Method for maintaining a driver-independent braking intervention after a collision
  Randomly Featured Patents
Outer rotor electric motor
Vacuum sealer
Needle and procedure for relieving urinary incontinence
Apparatus and method for winding a roving onto a bobbin
Antiestrogen therapy for symptoms of estrogen deficiency
Effective block extraction unit and method, and a circuit simulator
Steam generator having feed-water preheater
Memory device of SRAM type
Housing for a paper shredder
Vehicle speedometer metric conversion label