Resources Contact Us Home
Method for creating tensile strain by applying stress memorization techniques at close proximity to the gate electrode

Image Number 5 for United States Patent #8129236.

After forming the outer drain and source regions of an N-channel transistor, the spacer structure may be removed on the basis of an appropriately designed etch stop layer so that a rigid material layer may be positioned more closely to the gate electrode, thereby enhancing the overall strain-inducing mechanism during a subsequent anneal process in the presence of the material layer and providing an enhanced stress memorization technique (SMT). In some illustrative embodiments, a selective SMT approach may be provided.

  Recently Added Patents
Intelligent and automated code deployment
Video recording and playing apparatus and its control method
Real-time demand prediction in a fast service restaurant environment
Memory management configuration
Simultaneous enhancement of transmission loss and absorption coefficient using activated cavities
Power device and method of packaging same
System for controlled release of an active principle and method for preparation
  Randomly Featured Patents
Front bicycle derailleur
Method and apparatus for network communications over HDMI in standby mode
Dental compositions with zinc and bicarbonate salts
Three-dimensionally embodied circuit with electrically connected semiconductor chips
Pipe connector load element
Internet protocol telephony security architecture
Elastic cord with adjustable loop
Non-interfering on-line receiver test system
Method of concentrating slave terminals to be hunted in a packet switching communication pattern using a master key number