Resources Contact Us Home
Method for creating tensile strain by applying stress memorization techniques at close proximity to the gate electrode

Image Number 5 for United States Patent #8129236.

After forming the outer drain and source regions of an N-channel transistor, the spacer structure may be removed on the basis of an appropriately designed etch stop layer so that a rigid material layer may be positioned more closely to the gate electrode, thereby enhancing the overall strain-inducing mechanism during a subsequent anneal process in the presence of the material layer and providing an enhanced stress memorization technique (SMT). In some illustrative embodiments, a selective SMT approach may be provided.

  Recently Added Patents
Haloalky -substituted amides as insecticides and acaricides
System and method of creating and providing SMS http tagging
Per-request control of DNS behavior
Rose plant named `Esm R068`
Image forming apparatus
Viewing stand
Method and apparatus for performing real time anomaly detection
  Randomly Featured Patents
Wheelchair braking apparatus
Error logging memory system for avoiding miscorrection of triple errors
Process for producing a .beta.-lactone derivative
Printer controller, printing system, and recording medium therefor
Substrate processing apparatus and method
Field effect transistor
Thermal radiation facelift device
Gauge for mounting window-shade brackets
Speculative directory lookup for sharing classification
Light fixture