Resources Contact Us Home
Method for creating tensile strain by applying stress memorization techniques at close proximity to the gate electrode

Image Number 5 for United States Patent #8129236.

After forming the outer drain and source regions of an N-channel transistor, the spacer structure may be removed on the basis of an appropriately designed etch stop layer so that a rigid material layer may be positioned more closely to the gate electrode, thereby enhancing the overall strain-inducing mechanism during a subsequent anneal process in the presence of the material layer and providing an enhanced stress memorization technique (SMT). In some illustrative embodiments, a selective SMT approach may be provided.

  Recently Added Patents
Input system including position-detecting device
Build process management system
Method of fabricating crystal unit, crystal unit fabrication mask, and crystal unit package
Reception circuit and signal reception method
Bessel beam plane illumination microscope
Apparatus and method for controlling a tunable matching network in a wireless network
  Randomly Featured Patents
Method and device for reorganizing data in a memory system, in particular for control devices in motor vehicles
RF electrode array for low-rate collagen shrinkage in capsular shift procedures and methods of use
Refueling system
System for providing targeted internet information to mobile agents
Optical data recording disc and system
Soap holding device having design imprinter
Reduced-pressure drying unit and coating film forming method
Air bag system for protecting the knees of a driver
Methods and systems for efficient query rewriting
Hydrogen-permeable membrane and manufacturing method of the same