Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Method for creating tensile strain by applying stress memorization techniques at close proximity to the gate electrode










Image Number 5 for United States Patent #8129236.

After forming the outer drain and source regions of an N-channel transistor, the spacer structure may be removed on the basis of an appropriately designed etch stop layer so that a rigid material layer may be positioned more closely to the gate electrode, thereby enhancing the overall strain-inducing mechanism during a subsequent anneal process in the presence of the material layer and providing an enhanced stress memorization technique (SMT). In some illustrative embodiments, a selective SMT approach may be provided.








 
 
  Recently Added Patents
Processor and data transfer method
Systems and methods for tracking power modulation
Method and system for providing magnetic junctions having improved characteristics
Active pulse blood constituent monitoring
System and method for netbackup data decryption in a high latency low bandwidth environment
Charged particle beam apparatus
Traveling vehicle system and self-diagnosis method for the traveling vehicle system
  Randomly Featured Patents
Camera flash module and method for controlling same
Phase change memory
Connection point
End connector for floating oil boom
Personal cleansing freezer bar with selected fatty acid soaps and synthetic surfactant for reduced bathtub ring, improved mildness, and good lather
Device for the thermal treatment of unshelled eggs
Play cube
Compact and durable encasement for a digital radiography detector
Agricultural implement having field and transport modes
Variable gain amplifier