Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Migration management based on destination performance information










Image Number 14 for United States Patent #8127092.

Implementing migration of a computer or data in consideration of the performance of an entire computer system is disclosed. A management computer is coupled to a computer 41000 and to a storage system 51000 having RAID groups 51220 and 51221 for providing logical volumes 51210 to 51212. When a predetermined event occurs at a resource on an I/O path from the computer 41000 to the RAID groups 51220 and 51221, the applicable I/O path is extracted. Moreover, it is determined whether or not there is another I/O path used by another computer and another logical volume, which does not share any resources and does not use the extracted I/O path. When there is the other I/o path, it is determined whether or not a performance of a resource contained therein remains within a preset range of a threshold requirement in the case of migrating the computer 41000 and the logical volumes 51210 to 51212 to the other I/O path. If the performance falls within the range, the other I/O path is determined as a migration destination.








 
 
  Recently Added Patents
Coil-type electronic component and its manufacturing method
Method for forming a microstructure
Devices, methods, and graphical user interfaces for accessibility via a touch-sensitive surface
Vertical capacitive depletion field effect transistor
Automatically enabling the forwarding of instant messages
Datacenter utilizing modular infrastructure systems and redundancy protection from failure
Process for welding electrical connectors and welding device thereof
  Randomly Featured Patents
Zoom lens system
Multiple chamber container for delivering liquid under pressure
Electric connector
Palatable chewable tablet
Polarization optical system and projection-type liquid-crystal display device
Articulating clip applier cartridge
Sheet feeding method and apparatus
Battery disconnect switch
Multi-threaded packet processing architecture with global packet memory, packet recirculation, and coprocessor
Circuits systems and methods for power digital-to-analog converter protection