Image Number 3 for United States Patent #8125073.
A semiconductor device has a wafer for supporting the device and a conductive layer formed over a top surface of the wafer. A carrier wafer is permanently bonded over the conductive layer. Within the wafer and the carrier wafer, an interconnect structure is formed. The interconnect structure includes a first via formed in the wafer that exposes the conductive layer, a second via formed in the carrier wafer that exposes the conductive layer, a first metal layer deposited over the first via, the first metal layer in electrical contact with the conductive layer, and a second metal layer deposited over the second via, the second metal layer in electrical contact with the conductive layer. First and second insulation layers are deposited over the first and second metal layers respectively. The first or second insulation layer has an etched portion to expose a portion of the first or second metal layer.