Resources Contact Us Home
Transparent test method and scan flip-flop

Image Number 11 for United States Patent #8122413.

Logic blocks for IC designs (including gate-array, standard cell, or logic array designs) provide Design-for-Test-enabled flip-flops (DFT-enabled FFs) that inherently insure compliance with DFT rules associated with scan shifting. Test scan-chains are configured by daisy-chaining instances of the logic block in a transparent (invisible) manner to user-designed application circuits, which can be designed without any user-inserted test structures or other regard for DFT considerations. User asynchronous set and reset inputs and all Stuck-At faults on all user pins on these DFT-enabled FFs are observable via capture and scan-out. A first type of these DFT-enabled FFs features addressable control to partition test the application circuit. A second type of these DFT-enabled FFs features integral capture buffering that eliminates the need for partition test, simplifying control logic and reducing the number of test vectors needed.

  Recently Added Patents
Deflection device for a scanner with Lissajous scanning
Method and system for dynamic storage tiering using allocate-on-write snapshots
Plants and seeds of corn variety CV092363
Breathing mask
Method for programming non-volatile memory device and apparatuses performing the method
Terminal and method of controlling the same
Resist underlayer film forming composition for lithography, containing aromatic fused ring-containing resin
  Randomly Featured Patents
Folding user interface
Electrostatic discharge structure for 3-dimensional integrated circuit through-silicon via device
Train wheel bearing temperature detection
One piece molded device
Continuous platform cutting apparatus for cutting a cellular polymer surface
Base for a television set
Lipids with plasmin inhibitory properties
Catheter with spiral cut transition member
Probe connector
Polarizing illumination device and projection display device