Resources Contact Us Home
Transparent test method and scan flip-flop

Image Number 11 for United States Patent #8122413.

Logic blocks for IC designs (including gate-array, standard cell, or logic array designs) provide Design-for-Test-enabled flip-flops (DFT-enabled FFs) that inherently insure compliance with DFT rules associated with scan shifting. Test scan-chains are configured by daisy-chaining instances of the logic block in a transparent (invisible) manner to user-designed application circuits, which can be designed without any user-inserted test structures or other regard for DFT considerations. User asynchronous set and reset inputs and all Stuck-At faults on all user pins on these DFT-enabled FFs are observable via capture and scan-out. A first type of these DFT-enabled FFs features addressable control to partition test the application circuit. A second type of these DFT-enabled FFs features integral capture buffering that eliminates the need for partition test, simplifying control logic and reducing the number of test vectors needed.

  Recently Added Patents
String changing tool with a quick connector assembly and worm gear string cutter
Method for increasing expression of active tumor necrosis factor receptor family member-Ig fusion proteins
Hybrid asynchronous transmission process
Communication system including relay station and data frame for the communication system
Apparatus and method for adapted deblocking filtering strength
Changing a system clock rate synchronously
Method, system, and computer program product for scoring theoretical peptides
  Randomly Featured Patents
Flow system with pressure level interlock control apparatus
Bale grinder
Multi-composite acoustic panel
Error reporting and technical support customization for computing devices
Piezoelectric transformer, piezoelectric transformer drive circuit, piezoelectric transformer drive method and cold cathode tube drive apparatus using piezoelectric transformer
Resin vessel conveying system
Curing agents for epoxy-based polymers
Process for blending of ink used in counterfeit detection systems
Load balancing on disk array storage device
Differential nonmetals thickness gauge