Resources Contact Us Home
Transparent test method and scan flip-flop

Image Number 11 for United States Patent #8122413.

Logic blocks for IC designs (including gate-array, standard cell, or logic array designs) provide Design-for-Test-enabled flip-flops (DFT-enabled FFs) that inherently insure compliance with DFT rules associated with scan shifting. Test scan-chains are configured by daisy-chaining instances of the logic block in a transparent (invisible) manner to user-designed application circuits, which can be designed without any user-inserted test structures or other regard for DFT considerations. User asynchronous set and reset inputs and all Stuck-At faults on all user pins on these DFT-enabled FFs are observable via capture and scan-out. A first type of these DFT-enabled FFs features addressable control to partition test the application circuit. A second type of these DFT-enabled FFs features integral capture buffering that eliminates the need for partition test, simplifying control logic and reducing the number of test vectors needed.

  Recently Added Patents
Nutritional supplement method
Email certificates
Writing implement
Power semiconductor module
Method and apparatus for providing charging status information to subscriber of communication service
Epitaxial substrate for electronic device, in which current flows in lateral direction and method of producing the same
Bluetooth headset
  Randomly Featured Patents
Area security light with adaptable mounting hardware
Combination of bisphosphonate and tetracycline
Deburring tool
Desalination subsurface feedwater supply and brine disposal
Flock delivery systems
Power supply system
Glass substrates and methods of annealing the same
Super junction / resurf LDMOST (SJR-LDMOST)
Method and apparatus for audio bass enhancement using stereo speakers