Resources Contact Us Home
Transparent test method and scan flip-flop

Image Number 11 for United States Patent #8122413.

Logic blocks for IC designs (including gate-array, standard cell, or logic array designs) provide Design-for-Test-enabled flip-flops (DFT-enabled FFs) that inherently insure compliance with DFT rules associated with scan shifting. Test scan-chains are configured by daisy-chaining instances of the logic block in a transparent (invisible) manner to user-designed application circuits, which can be designed without any user-inserted test structures or other regard for DFT considerations. User asynchronous set and reset inputs and all Stuck-At faults on all user pins on these DFT-enabled FFs are observable via capture and scan-out. A first type of these DFT-enabled FFs features addressable control to partition test the application circuit. A second type of these DFT-enabled FFs features integral capture buffering that eliminates the need for partition test, simplifying control logic and reducing the number of test vectors needed.

  Recently Added Patents
Tag-based apparatus and methods for neural networks
Single integrated circuit configured to operate both a capacitive proximity sensor device and a resistive pointing stick
Estrogen receptor ligands
Maize variety X00C175
Polymer composites having highly dispersed carbon nanotubes
Pet fish burial pod
Sports helmet
  Randomly Featured Patents
Heated mitten
Seismic data acquisition
Controlled dilution system for drinking water and unit therefor
Plier-type tool
Liquid distribution unit and absorbent product having the same
Heart compressor with and without a cup
Robot apparatus, control method for robot apparatus, and toy for robot apparatus
Wood accelerating drying process based on its rheological properties
Method and apparatus for punch and place inserts for manufacture of oxygen sensor
Attribute-based identification schemes for objects in internet of things