Resources Contact Us Home
On chip timing adjustment in multi-channel fast data transfer

Image Number 6 for United States Patent #8122395.

A method and structure for an apparatus for maintaining signal integrity between integrated circuits residing on a printed circuit board. The apparatus has adjustable delay circuitry within the circuits and the adjustable delay circuitry adjusts the timing of signals processed within the circuit. A phase monitor connects to the circuits. The phase monitor detects phase differences between signals output by the circuits. A controller connected to the delay circuitry, the phase monitor, and the controller adjust the delay circuitry to compensate for the phase differences.

  Recently Added Patents
Calcium carbonate granulation
Method and apparatus for managing backup channel in multi-channel environment
Coated article and method for making the same
System and method for configuring a direct lift control system of a vehicle
Digital video disc player
Charge domain filter and method thereof
Composite materials comprising aggregate and an elastomeric composition
  Randomly Featured Patents
Method and apparatus for aligning and comparing images of the face and body from different imagers
Identification and placement of new virtual machines to reduce memory consumption based on shared images with hosted virtual machines
Metallic sulphide catalysts, processes for synthesising said catalysts and use thereof
Coupling assembly
Holographic recording and reproducing apparatus
Method for manufacturing reflective spatial light modulator mirror devices
Fire extinguishing device
Method and apparatus for effecting immunological analysis
OpenFlow communication system and OpenFlow communication method
Logic analyzer