Resources Contact Us Home
On chip timing adjustment in multi-channel fast data transfer

Image Number 6 for United States Patent #8122395.

A method and structure for an apparatus for maintaining signal integrity between integrated circuits residing on a printed circuit board. The apparatus has adjustable delay circuitry within the circuits and the adjustable delay circuitry adjusts the timing of signals processed within the circuit. A phase monitor connects to the circuits. The phase monitor detects phase differences between signals output by the circuits. A controller connected to the delay circuitry, the phase monitor, and the controller adjust the delay circuitry to compensate for the phase differences.

  Recently Added Patents
Mobile electronic device
Tiger paw stationary tab
Campanula plant named `PKMM03`
Computerized information and display methods
Method and device for managing a turning setpoint applied to at least one turning actuator for the rear wheels of an automobile
Co-map communication operator
  Randomly Featured Patents
Noise cancel circuit
Cam operated cutoff machine
Power transmission chain and power transmission apparatus
Sulfite or bisulfite hair-waving composition containing a wave accelerating agent
Phase locked loop frequency generating circuit and a receiver using the circuit
Load center
Method of producing thin layer methanation reaction catalyst
Joint sealing structure
Magneto-optical recording/reproducing system having an electromagnetic actuator
Image-forming device and scanning unit for use therein