Resources Contact Us Home
On chip timing adjustment in multi-channel fast data transfer

Image Number 6 for United States Patent #8122395.

A method and structure for an apparatus for maintaining signal integrity between integrated circuits residing on a printed circuit board. The apparatus has adjustable delay circuitry within the circuits and the adjustable delay circuitry adjusts the timing of signals processed within the circuit. A phase monitor connects to the circuits. The phase monitor detects phase differences between signals output by the circuits. A controller connected to the delay circuitry, the phase monitor, and the controller adjust the delay circuitry to compensate for the phase differences.

  Recently Added Patents
Materials for organic electroluminescent devices containing substituted 10-benzo[c]phenanthrenes
System for controlled release of an active principle and method for preparation
Transistor and display device
Portable gaming device and gaming system combining both physical and virtual play elements
Sports helmet
Electric discharge machining hole drilling
Anti-infective derivatives, method for the production thereof, pharmaceutical compositions containing same and uses of said derivatives in treatment
  Randomly Featured Patents
Liquid sample analyser
Liquid crystal display and method of inspecting the same
System and method for printing and error correction of hangul barcode
NOR flash memory and method of manufacturing the same
Method for visually confirming a relationship between an edited packet and serial data
Semiconductor device having a dielectric film and a fabrication process thereof
CMOS processing employing zero degree halo implant for P-channel transistor
Current controlled inverter
Hockey stick with tapered hosel
Oil drainage coupler