Resources Contact Us Home
Write-leveling implementation in programmable logic devices

Image Number 7 for United States Patent #8122275.

Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device.

  Recently Added Patents
Electric power steering apparatus
Color variation control process for molding plastic and composite multi-color articles
Picture information coding device and coding method
Compounds, compositions and methods for reducing lipid levels
Method for the treatment, alleviation of symptoms of, relieving, improving and preventing a cognitive disease, disorder or condition
Luggage cart
  Randomly Featured Patents
Foot support device
Method for inspecting integrated circuits or other objects
Method of and apparatus for image smoothing along a tangential direction of a contour
EUV mask blank defect mitigation
High-gain bipolar junction transistor compatible with complementary metal-oxide-semiconductor (CMOS) process and method for fabricating the same
System and method for searching and matching databases
Movable track assembly for drive tracks
Absorbent article having tucked flaps
Floating docks
Brain-wave aware sleep management