Resources Contact Us Home
Write-leveling implementation in programmable logic devices

Image Number 7 for United States Patent #8122275.

Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device.

  Recently Added Patents
Method for treating wounds for mammals, wound healer compound, and method of manufacturing thereof
Cell transport system comprising a homogeneous mixture of agarose and agarase
System and method for multi-tiered meta-data caching and distribution in a clustered computer environment
Weak acid recovery system for ethanol separation processes
Method and computer system for automatic vectorization of a vessel tree
Information recording medium and information processing method for accessing content with license or copyright protection
  Randomly Featured Patents
Multiply-accumulate (MAC) unit for single-instruction/multiple-data (SIMD) instructions
Method of making a sand mold
Apparatus for a band clamping tool
Switchboards and panelboards having interlock and load selection capabilities
Elbow-making machine
Resource isolation using reinforcement learning and domain-specific constraints
Instrument having ultra-thin conductive coating and method for magnetic resonance imaging of such instrument
Method for managing shared tasks in a multi-tasking data processing system
Multiple choices mathematical game apparatus
Apparatus for measuring visual performance