Resources Contact Us Home
Write-leveling implementation in programmable logic devices

Image Number 7 for United States Patent #8122275.

Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device.

  Recently Added Patents
Electrical event detection device and method of detecting and classifying electrical power usage
Vehicle and communication monitoring
Message value indicator
Washing-up bowl
Cooking device and method of manufacture of the same
Visualization of information associated with applications in user interfaces
Wrench head
  Randomly Featured Patents
Rocker assembly with interconnectable arms
Surface treatment composition and preparation thereof
Variable length coding method and variable length decoding method
Storage unit and storage unit subsystem
Electrolyte for aluminum electrolytic capacitor
Connector equipped with dust-proof arrangement, and a set of dust-proof hoods for connector
Liquid-metal ion beam source substructure
Gaming device having multiplier poker game
Cleaning and polishing composition