Resources Contact Us Home
Write-leveling implementation in programmable logic devices

Image Number 7 for United States Patent #8122275.

Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device.

  Recently Added Patents
Constant low-flow air source control system and method
Semiconductor device
Driver circuit for driving semiconductor switches
Blend polymer gas separation membrane
Stroboscopic light source for a transmitter of a large scale metrology system
Pipe coupling
Optical writer and image forming apparatus including same
  Randomly Featured Patents
Semiconductor memory device operable to write data accurately at high speed
Phthalocyanine compounds and anti-microbial use
Downflow fluid catalytic cracking process and apparatus
Process for the indigo dyeing of yarns in skeins
Angled vehicle crash sensor
Jet pump assembly
Multilayer integrated assembly having an integral microminiature valve
Catalyst, method for catalyst manufacture and use
Wireless communication device
Multipurpose antirust and friction reducing additives and compositions thereof