Resources Contact Us Home
Method of manufacturing a semiconductor device having an active region and dummy patterns

Image Number 15 for United States Patent #8119495.

There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP.sub.1 of relatively wider area and the second dummy pattern DP.sub.2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP.sub.1 occupy a relatively wide region among the dummy region FA.

  Recently Added Patents
Battery-operated massager and soap dispensing wand
Mechanical and moisture protection apparatus for electronic devices
Modular connector for touch sensitive device
Dynamic data filtering system and method
System and method for confirming delivery of an electronic message
Gyroscope utilizing torsional springs and optical sensing
Method of manufacturing crystalline silicon solar cells with improved surface passivation
  Randomly Featured Patents
System, computer program product and method for managing documents
Multi-element LED lamp package
Axial wafer tumbler lock and key
Multiple layer directionally oriented nonwoven fiber material and methods of manufacturing same
MIMO transmission and reception methods and devices
Net rucker
Virtual bookshelf
Two-stage extruder
Composition of polyarylenesulfide, bisphenol epoxy resin and oxazoline-containing amorphous polymer