Resources Contact Us Home
High performance capacitors in planar back gates CMOS

Image Number 3 for United States Patent #8119474.

A method of manufacture and device for a dual-gate CMOS structure. The structure includes a first plate in an insulating layer and a second plate above the insulating layer electrically corresponding to the first plate. An isolation structure is between the first plate and the second plate.

  Recently Added Patents
Camera body, and camera system
Wire catalyst for hydrogenation/dehydrogenation reaction and manufacturing method therefor
Image scanning apparatus and image forming apparatus
Cable preparation tool
System and method for computational unification of heterogeneous implicit and explicit processing elements
Electronic control apparatus
Wireless enclosure
  Randomly Featured Patents
Method and device for blow molding workpieces by means of a blowing-stretching mandrel having special air delivery ports
Electrodialysis of salts for producing acids and bases
Semiconductor device and manufacturing method of the same
Pattern inspection apparatus and method
Panel structure for a portable panel saw
Road map data generation apparatus, road map data generation system, and method for generating road map data
Tray surface cleaning device
Gas generation dispenser method for on-demand fluid delivery
Rack merchandising system
Seat belt apparatus for vehicle