Resources Contact Us Home
High performance capacitors in planar back gates CMOS

Image Number 3 for United States Patent #8119474.

A method of manufacture and device for a dual-gate CMOS structure. The structure includes a first plate in an insulating layer and a second plate above the insulating layer electrically corresponding to the first plate. An isolation structure is between the first plate and the second plate.

  Recently Added Patents
Light emitting device and light emitting device package
Display panel and gate driving circuit and driving method for gate driving circuit
Image processing apparatus, image printing apparatus and printing data generation method
Negative electrode material for non-aqueous electrolyte secondary battery, method for manufacturing negative electrode material for non-aqueous electrolyte secondary battery, non-aqueous elect
System and method for testing an integrated circuit embedded in a system on a chip
Systems of an electronic device and methods for manufacturing the same
  Randomly Featured Patents
Semiconductor laser
Method of manufacturing low contaminant wiper
Pickup device for optical disk drive
Collapsible frame
Rolled glove pair having circumscribing binding
Vertical annular separation and pumping system with outer annulus liquid discharge arrangement
Decoupled switched current temperature circuit with compounded .DELTA.V
Service seal unit for well packer
Color reproduction evaluation apparatus and program storage medium
Still video device that records/reproduces a plurality of identical signals