Resources Contact Us Home Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE     High performance capacitors in planar back gates CMOS Image Number 3 for United States Patent #8119474. A method of manufacture and device for a dual-gate CMOS structure. The structure includes a first plate in an insulating layer and a second plate above the insulating layer electrically corresponding to the first plate. An isolation structure is between the first plate and the second plate.       Recently Added Patents Booster seat assembly Continuous curding machine for tofu products Optical film, image display device, diethynylfluorene, and polymer thereof Eyeliner applicator Reaction vessel and reaction controller Solid polymer electrolytes based on triblock copolymers, especially polystyrene-poly(oxyethylene)-polystyrene Display screen with icon   Randomly Featured Patents Optical information recording method, optical information recording apparatus and optical information recording medium 1 to 2.sup.N-1 fractional divider circuit with fine fractional resolution Medical fastener strap Systems and methods for constructive-dialogic learning Enclosed shelter for storing boats and life rafts in marine structures Pedal anchoring cleats on a sole of a cycling shoe Recording device, recording medium recording method, and program for recording medium recording method Pressurized lead-in for a seismic streamer cable Electronic counter for incremental measuring device Non-inverting domino register © 2006-2008 PatentGenius. All Rights Reserved.