Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
High performance capacitors in planar back gates CMOS










Image Number 3 for United States Patent #8119474.

A method of manufacture and device for a dual-gate CMOS structure. The structure includes a first plate in an insulating layer and a second plate above the insulating layer electrically corresponding to the first plate. An isolation structure is between the first plate and the second plate.








 
 
  Recently Added Patents
Push mechanism for efficiently sending aggregated data items to client
Subscribing to content
Thiocyanato or isothiocyanato substituted naphthalene diimide and rylene diimide compounds and their use as n-type semiconductors
Method and system for physical verification using network segment current
Touch screen guitar
Information storage medium, reproducing method, and recording method
Method for the hydrolysis of substituted formylamines into substituted amines
  Randomly Featured Patents
System and method for highly reliable data replication
MEMS biaxial resonant accelerometer
Process for the production of carbodiimides and carbodiimide-isocyanate adducts
Rinse screen for a water bucket
Centrifugal blower
Rescuing trusted nodes from filtering of untrusted network entities
Shoe lace fastening system
Shape adjusting tool
Portable, removably attached speaker assembly
Data word indicator in a system for assembling transport data packets