Resources Contact Us Home
High performance capacitors in planar back gates CMOS

Image Number 3 for United States Patent #8119474.

A method of manufacture and device for a dual-gate CMOS structure. The structure includes a first plate in an insulating layer and a second plate above the insulating layer electrically corresponding to the first plate. An isolation structure is between the first plate and the second plate.

  Recently Added Patents
System for in vivo analysis of tear film in the human eye via phase shifting interferometry
Medical implant and method for secure implant communication
Non-inertial safe and arm device
Use of certificate authority to control a device's access to services
Polyhydroalkanoate composition exhibiting improved impact resistance
System for inspecting surface defects of a specimen and a method thereof
Method for the operation of a transverse guiding driver assist system of a motor vehicle, and motor vehicle
  Randomly Featured Patents
Polymeric films
Ingot mold
Methods for reducing or preventing transplant rejection in the eye and intraocular implants for use therefor
Disubstituted phthalazine hedgehog pathway antagonists
Electromechanical regulator with primary and backup modes of operation for regulating passenger oxygen
Damping of LC ringing in IC (integrated circuit) power distribution systems
Automatic conversion of source code from 32-bit to 64-bit
Broom and tool holder mountable on a planar vertical surface
Optical apparatus, exposure apparatus using the same, and gas introduction method
Lockable hinge