Resources Contact Us Home
High performance capacitors in planar back gates CMOS

Image Number 3 for United States Patent #8119474.

A method of manufacture and device for a dual-gate CMOS structure. The structure includes a first plate in an insulating layer and a second plate above the insulating layer electrically corresponding to the first plate. An isolation structure is between the first plate and the second plate.

  Recently Added Patents
Cell proliferation inhibitor
Passive charge cord release system for an electric vehicle
Display apparatus
Interest point detection
Apparatus with a local timing circuit that generates a multi-phase timing signal for a digital signal processing circuit
Toy ball
Systems and methods for mitigating spectral regrowth from non-linear systems
  Randomly Featured Patents
System and method for managing server configurations
Pick-up style utility vehicle with adjustable cargo bed
Apparatus and method for determining read head position
Method and apparatus for location marking
Head suspension assembly for hard disk drive
Wavelength selective optical devices using optical directional coupler
Housing and actuating apparatus and methods associated therewith
Track rail
Grinding apparatus for a condiment grinder
Moving image compression-coding device, method of compression-coding moving image, and H.264 moving image compression-coding device