Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
High performance capacitors in planar back gates CMOS










Image Number 3 for United States Patent #8119474.

A method of manufacture and device for a dual-gate CMOS structure. The structure includes a first plate in an insulating layer and a second plate above the insulating layer electrically corresponding to the first plate. An isolation structure is between the first plate and the second plate.








 
 
  Recently Added Patents
Energy drink package
Materials for organic electroluminescent devices containing substituted 10-benzo[c]phenanthrenes
Solid-state imaging device and electronic apparatus with antireflection structure
Nuclear reactor building and construction method thereof
Apparatus and method for scrolling a screen of a portable terminal having a touch screen
Information processing apparatus and method
Switching device and electronic apparatus using the same
  Randomly Featured Patents
System and method for implementing a service adapter
Stock trading limit order coupled link (LOCK)
Exposure equipment
Hybrid operating mode for DISI engines
Method of forming an array of emmitter tips
Apparatus and method for controlling the air flow into an engine
Techniques for reworking circuit boards with ni/au finish
Speech recognition system for mobile terminal
Operating system for a multi-tasking operating environment
Water reducible epoxy ester using monocarboxylic acid to control molecular weight