Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Transactional memory system which employs thread assists using address history tables










Image Number 14 for United States Patent #8117403.

A computing system uses specialized "Set Associative Transaction Tables" and additional "Summary Transaction Tables" to speed the processing of common transactional memory conflict cases and those which employ assist threads using an Address History Table and processes memory transactions with a Transaction Table in memory for parallel processing of multiple threads of execution by support of which an application need not be aware. Special instructions may mark the boundaries of a transaction and identify memory locations applicable to a transaction. A `private to transaction` (PTRAN) tag, directly addressable as part of the main data storage memory location, enables a quick detection of potential conflicts with other transactions that are concurrently executing on another thread of said computing system. The tag indicates whether (or not) a data entry in memory is part of a speculative memory state of an uncommitted transaction that is currently active in the system.








 
 
  Recently Added Patents
Sheet member and method of manufacturing sheet member
Communication network management system, method and program, and management computer
Etching apparatus and methods
Towel clip
Method and system for automatically hiding irrelevant parts of hierarchical structures in computer user interfaces
Polypropylene bottles
Electrode and method for manufacturing the same
  Randomly Featured Patents
System and method for managing requests for pooled resources during non-contention
Method and apparatus for physical fitness training
Augmented I/O for limited form factor user-interfaces
Method, an electrical system, a digital control module, and an actuator control module in a vehicle
Capacitor structures, DRAM cell structures, and integrated circuitry, and methods of forming capacitor structures, integrated circuitry and DRAM cell structures
Modifying agents for polyolefins
Method for controlling an adjustment process of a part
Processor
Arm training device
Multi-state magnetoresistance random access cell with improved memory storage density