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Memory module capable of improving the integrity of signals transmitted through a data bus and a command/address bus, and a memory system including the same










Image Number 6 for United States Patent #8117363.

A memory module and a related memory system are disclosed. The memory module comprises a semiconductor memory having a data output buffer, a data input buffer, a command/address input buffer and a first termination resistor unit connected to a data bus. The memory module further comprises a second termination resistor unit connected to an internal command/address bus. First and second termination resistor units are preferably of different resistive value and/or type.








 
 
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