Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Fully-buffered dual in-line memory module with fault correction










Image Number 18 for United States Patent #8103921.

A memory system including a first memory, a content addressable memory, a testing module, and a memory controller. The first memory includes first memory cells. The content addressable memory includes second memory cells and is configured to store addresses of selected ones of the first memory cells, store data having the addresses in corresponding ones of the second memory cells, and retrieve the data from the corresponding ones of the second memory cells. The testing module is configured to determine a number of the first memory cells that fail at a first refresh rate. The first refresh rate corresponds to a time period between refreshing the first memory cells. The memory controller is configured to, based on the number of the first memory cells that fail at the first refresh rate, maintain the first refresh rate, and increase the first refresh rate.








 
 
  Recently Added Patents
Reference circuit with curvature correction using additional complementary to temperature component
Tetrazolyl oxime derivative, salt thereof, and plant disease control agent
Method and apparatus for band switching in wireless local access network
System and method for enhanced artificial bandwidth expansion
Pausing a VoiceXML dialog of a multimodal application
Network fault detection
Method and system for security authentication of radio frequency identification
  Randomly Featured Patents
Queuing apparatus and method for a cordless communication transceiver
System and method for the production or handling of heavy oil
Liquid crystal panel and liquid crystal display apparatus
Tetraalkyl titanate modified nylon magnet wire insulation coating
Parameter estimator for a multiuser detection receiver
Method for applying pesticides and repellents
Foldable shelter
Fuse
Method and apparatus for perforating corrugated tubing
Programmable coding and decoding arrangement