Resources Contact Us Home
Fully-buffered dual in-line memory module with fault correction

Image Number 18 for United States Patent #8103921.

A memory system including a first memory, a content addressable memory, a testing module, and a memory controller. The first memory includes first memory cells. The content addressable memory includes second memory cells and is configured to store addresses of selected ones of the first memory cells, store data having the addresses in corresponding ones of the second memory cells, and retrieve the data from the corresponding ones of the second memory cells. The testing module is configured to determine a number of the first memory cells that fail at a first refresh rate. The first refresh rate corresponds to a time period between refreshing the first memory cells. The memory controller is configured to, based on the number of the first memory cells that fail at the first refresh rate, maintain the first refresh rate, and increase the first refresh rate.

  Recently Added Patents
Method of operating an electromechanical converter, a controller and a computer program product
Display screen of a mobile terminal or portion thereof with a graphical user interface
Device and method for adjusting a chrominance signal based on an edge strength
Vehicle and communication monitoring
Color imaging device
Power generating apparatus of renewable energy type and method of attaching and detaching blade
Helmet mandible
  Randomly Featured Patents
Pressure plate assembly for a friction clutch
Method and system for efficient data transmission with server side de-duplication
Grapevine `90-3437`
Facsimile telecommunications system and method
Pin visor
Tetra-aza-heterocycles as phosphatidylinositol-3-kinases (P13-kinases) inhibitor
Method and system for pattern recognition and processing
Apparatus and methods for restacking fanfolded continuous form paper output from a printer
Rotating wheel return mechanism