Resources Contact Us Home
Fully-buffered dual in-line memory module with fault correction

Image Number 11 for United States Patent #8103921.

A memory system including a first memory, a content addressable memory, a testing module, and a memory controller. The first memory includes first memory cells. The content addressable memory includes second memory cells and is configured to store addresses of selected ones of the first memory cells, store data having the addresses in corresponding ones of the second memory cells, and retrieve the data from the corresponding ones of the second memory cells. The testing module is configured to determine a number of the first memory cells that fail at a first refresh rate. The first refresh rate corresponds to a time period between refreshing the first memory cells. The memory controller is configured to, based on the number of the first memory cells that fail at the first refresh rate, maintain the first refresh rate, and increase the first refresh rate.

  Recently Added Patents
User interface for integrating applications on a mobile communication device
Distributive data capture
Methods and systems for determining the reliability of transaction
Monitoring agent programs in a distributed computing platform
Method and system for the assignment of security group information using a proxy
Browsing or searching user interfaces and other aspects
Managing and collaborating with digital content
  Randomly Featured Patents
Drugs for periodontal disease
Device and method for measuring the energy content of hot and humid air streams
Reader based on RFID
Pressure-sensitive writing stylus
Complexes of DNA and esters derived from daunorubicine, their preparation and use
Supporting device
Combined bottle and cap
Measuring apparatus with transmitter and receiver optically coupled with windshield surface
Method and apparatus for splitting a cathode ray tube