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Fully-buffered dual in-line memory module with fault correction










Image Number 11 for United States Patent #8103921.

A memory system including a first memory, a content addressable memory, a testing module, and a memory controller. The first memory includes first memory cells. The content addressable memory includes second memory cells and is configured to store addresses of selected ones of the first memory cells, store data having the addresses in corresponding ones of the second memory cells, and retrieve the data from the corresponding ones of the second memory cells. The testing module is configured to determine a number of the first memory cells that fail at a first refresh rate. The first refresh rate corresponds to a time period between refreshing the first memory cells. The memory controller is configured to, based on the number of the first memory cells that fail at the first refresh rate, maintain the first refresh rate, and increase the first refresh rate.








 
 
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