Resources Contact Us Home
Memory device bit line sensing system and method that compensates for bit line resistance variations

Image Number 7 for United States Patent #8102723.

Systems, devices and methods are disclosed, such as a system and method of sensing the voltage on bit lines that, when respective memory cells coupled to the bit lines are being read that compensates for variations in the lengths of the bit lines between the memory cells being read and respective bit line sensing circuits. The system and method may determine the length of the bit lines between the memory cells and the sensing circuits based on a memory address, such as a block address. The system and method then uses the determined length to adjust either a precharge voltage applied to the bit lines or the duration during which the bit lines are discharged by respective memory cells before respective voltages on the bit lines are latched.

  Recently Added Patents
Method for detection and characterization of a microorganism in a sample using time-dependent intrinsic fluorescence measurements
Methods for determining decoding order in a MIMO system with successive interference cancellation
Electrical conduit containing a fire-resisting thermoplastic composition
Gaming machine certificate creation and management
Lighting apparatus
Vending machine
  Randomly Featured Patents
Constrained-curve correlation model
Taste potentiator compositions and beverages containing same
Snowplough blade with adjustable width
Image exposure method using display panel
Method of alleviating withdrawal symptoms
Flowshot technique
Method for predicting continuous and discontinuous waveguide targets using interwell seismic signature characteristics
Hot deformation testing method and apparatus
Sealed lead-acid cell tray assembly and motive powered vehicle using such cell tray assembly