Resources Contact Us Home
Memory device bit line sensing system and method that compensates for bit line resistance variations

Image Number 7 for United States Patent #8102723.

Systems, devices and methods are disclosed, such as a system and method of sensing the voltage on bit lines that, when respective memory cells coupled to the bit lines are being read that compensates for variations in the lengths of the bit lines between the memory cells being read and respective bit line sensing circuits. The system and method may determine the length of the bit lines between the memory cells and the sensing circuits based on a memory address, such as a block address. The system and method then uses the determined length to adjust either a precharge voltage applied to the bit lines or the duration during which the bit lines are discharged by respective memory cells before respective voltages on the bit lines are latched.

  Recently Added Patents
Therapeutic compositions and methods
Stable file system
Zero-copy network and file offload for web and application servers
Method and apparatus for map transmission in wireless communication system
Front face of a vehicle wheel
Method and system for advertisement using internet browser to insert advertisements
Method and apparatus for laser strip splicing
  Randomly Featured Patents
Process for manufacturing hollow pastries
Plastic fitting assembly
Soybean cultivar 98179010
Organic supplier enablement based on a business transaction
Support vector regression for censored data
Six lamp capacity low profile light fixture
Induction heating device with a quick disconnect terminal and method of use
Water closet
Piston assembly having an outer skirt and a spaced inner core
African violet plant