Resources Contact Us Home
Memory device bit line sensing system and method that compensates for bit line resistance variations

Image Number 7 for United States Patent #8102723.

Systems, devices and methods are disclosed, such as a system and method of sensing the voltage on bit lines that, when respective memory cells coupled to the bit lines are being read that compensates for variations in the lengths of the bit lines between the memory cells being read and respective bit line sensing circuits. The system and method may determine the length of the bit lines between the memory cells and the sensing circuits based on a memory address, such as a block address. The system and method then uses the determined length to adjust either a precharge voltage applied to the bit lines or the duration during which the bit lines are discharged by respective memory cells before respective voltages on the bit lines are latched.

  Recently Added Patents
Pausing multimedia data streams
Light emitting device and light emitting device package
Browsing or searching user interfaces and other aspects
Data driver and liquid crystal display device using the same
Focus information generating device and focus information generating method
Systems and methods for mitigating spectral regrowth from non-linear systems
Burner grate
  Randomly Featured Patents
Seat back mounting system
Sand blasting apparatus
Mass interconnect system
In-situ sensor for automated measurements of gas content in liquid and related system and method
Motor driven variable optical attenuator
Winding control device for a take-up winder
In-mold coating compositions containing functional group terminated liquid polymers
Semiconductor memory device having an error correction function and associated method
Method and apparatus for determining internal status of a processor using simulation guided by acquired data
Method for processing solid or molten materials