Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Memory device bit line sensing system and method that compensates for bit line resistance variations










Image Number 7 for United States Patent #8102723.

Systems, devices and methods are disclosed, such as a system and method of sensing the voltage on bit lines that, when respective memory cells coupled to the bit lines are being read that compensates for variations in the lengths of the bit lines between the memory cells being read and respective bit line sensing circuits. The system and method may determine the length of the bit lines between the memory cells and the sensing circuits based on a memory address, such as a block address. The system and method then uses the determined length to adjust either a precharge voltage applied to the bit lines or the duration during which the bit lines are discharged by respective memory cells before respective voltages on the bit lines are latched.








 
 
  Recently Added Patents
Arrangements and method relating to communication bearers
Solar cell with hyperpolarizable absorber
Power supply device
Fast and compact circuit for bus inversion
Plate
Method and system for streaming digital video content to a client in a digital video network
Method and system for updating device management application meter read logic
  Randomly Featured Patents
Process for the preparation of self-swelling leakage-preventing materials
Depth sensing camera systems and methods
Safety chain saw guard cover
Device for exercising vaginal muscles
Enabling terminal services through a firewall
System and method for assignment of ATM virtual circuits to queues in a DSLAM
Process for fabricating capacitor
Method and apparatus for avoiding ribbon windings when winding a cross-wound bobbin
Image recording apparatus having tray guide
Toy shield