Resources Contact Us Home
Memory device bit line sensing system and method that compensates for bit line resistance variations

Image Number 7 for United States Patent #8102723.

Systems, devices and methods are disclosed, such as a system and method of sensing the voltage on bit lines that, when respective memory cells coupled to the bit lines are being read that compensates for variations in the lengths of the bit lines between the memory cells being read and respective bit line sensing circuits. The system and method may determine the length of the bit lines between the memory cells and the sensing circuits based on a memory address, such as a block address. The system and method then uses the determined length to adjust either a precharge voltage applied to the bit lines or the duration during which the bit lines are discharged by respective memory cells before respective voltages on the bit lines are latched.

  Recently Added Patents
Substrate processing apparatus and display method of substrate processing apparatus
Redistribution layer (RDL) with variable offset bumps
Real-time demand prediction in a fast service restaurant environment
Image reconstruction iterative method
Battery terminal with current sensor
Highly detectable pilot structure
Identifying conceptually related terms in search query results
  Randomly Featured Patents
Apparatus for cutting V-grooves in mats
Human disease modeling using somatic gene transfer
Forklift lever cover
Semiconductor light emitting device, its manufacturing method and optical recording and/or reproducing apparatus
Interleukin-6 splice variant
Machine for handling parts
Systems and methods for data indexing and processing
Central locking system for lockable entries of buildings or vehicles, particularly motor vehicles
In-dash compact disc retriever
Tablet cutter