Resources Contact Us Home
Memory device bit line sensing system and method that compensates for bit line resistance variations

Image Number 7 for United States Patent #8102723.

Systems, devices and methods are disclosed, such as a system and method of sensing the voltage on bit lines that, when respective memory cells coupled to the bit lines are being read that compensates for variations in the lengths of the bit lines between the memory cells being read and respective bit line sensing circuits. The system and method may determine the length of the bit lines between the memory cells and the sensing circuits based on a memory address, such as a block address. The system and method then uses the determined length to adjust either a precharge voltage applied to the bit lines or the duration during which the bit lines are discharged by respective memory cells before respective voltages on the bit lines are latched.

  Recently Added Patents
Device and method for generating soft tissue contrast images
Cascode circuit device with improved reverse recovery characteristic
Power storage device and method for manufacturing the same
Optical power measurement method, optical line terminal and optical network unit
Provision of downlink packet access services to user equipment in spread spectrum communication network
Systems and methods for managing and utilizing excess corn residue
Imaging device, method and computer readable medium
  Randomly Featured Patents
Sway control adaptor
Antenna, antenna device, and radio equipment
Machine tool
Drum head tensioning mechanism
Game apparatus having incentive producing means
Control device for the position control of a hydraulic cylinder unit comprising a linearization unit
Concrete vibrator machine
Nursing system