Resources Contact Us Home
Analog/digital converter and semiconductor integrated circuit device

Image Number 19 for United States Patent #8102289.

In the digital calibration technique of the conventional time-interleaved analog/digital converter, it is impossible to perform highly-accurate calibration that supports a high-speed sampling rate of the next-generation application and achieves a high resolution. For its solution, a reference A/D conversion unit is connected in parallel to an input common to a time-interleaved A/D converter to be a calibration target, and the output of each unitary A/D conversion unit which makes up the time-interleaved A/D converter is calibrated in a digital region by using a low-speed high-resolution A/D conversion result output from the reference A/D conversion unit. Also, fCLK/N (fCLK represents an overall sampling rate of the time-interleaved A/D converter, and N is relatively prime to the number of unitary A/D conversion units connected in parallel M) is set as the operation clock frequency of the reference A/D conversion unit. In this configuration, samplings of all unitary A/D conversion units can be sequentially synchronized with the sampling of the reference A/D conversion unit, and the operation clock frequency of the reference A/D converter can be made N times slower than the overall sampling rate of the time-interleaved A/D converter.

  Recently Added Patents
Cooking oven with energy saving mode and method
Circuit for compressing data and a processor employing same
Bull stationery tab
Authentication method
2,4-disubstituted pyrimidines useful as kinase inhibitors
Emergent information database management system
System and method for document orientation detection
  Randomly Featured Patents
Selective oxygen enrichment in slagging cyclone combustors
Valve handle
Method and apparatus for automatically populating a data warehouse system
Timeline application for log structured storage devices
Extraction process for recovery of rhenium
Circuit and method for implementing the advanced encryption standard block cipher algorithm in a system having a plurality of channels
Method and apparatus for determining classifier features with minimal supervision
Integrated translational land-grid array sockets and loading mechanisms for semiconductive devices
Optical beam scanner with detector position adjustment means