Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Method of enhancing lithography capabilities during gate formation in semiconductors having a pronounced surface topography










Image Number 6 for United States Patent #8101512.

In a mesa isolation configuration for forming a transistor on a semiconductor island, an additional planarization step is performed to enhance the uniformity of the gate patterning process. In some illustrative embodiments, the gate electrode material may be planarized, for instance, on the basis of CMP, to compensate for the highly non-uniform surface topography, when the gate electrode material is formed above the non-filled isolation trenches. Consequently, significant advantages of the mesa isolation strategy may be combined with a high degree of scalability due to the enhancement of the critical gate patterning process.








 
 
  Recently Added Patents
Method, system and computer program product for verifying floating point divide operation results
Lighting apparatus
Method for radiation sterilization of medical devices
Method and system for tracking mobile electronic devices while conserving cellular network resources
Method and apparatus for providing contention-based resource zones in a wireless network
Electronic device
Cap
  Randomly Featured Patents
Zero-voltage-switched multi-resonant converters including the buck and forward type
Coating lance centralizer
Method for providing removable weld backing
Method and apparatus for magnetic communication via a photographic filmstrip
Apparatus and method for securing resources shared by multiple operating systems
Steam turbine plant
Fuel injector
Plasmon resonance biosensor and method
Pharmaceutical pellet
Neo-tryptophan