Resources Contact Us Home
Method of enhancing lithography capabilities during gate formation in semiconductors having a pronounced surface topography

Image Number 6 for United States Patent #8101512.

In a mesa isolation configuration for forming a transistor on a semiconductor island, an additional planarization step is performed to enhance the uniformity of the gate patterning process. In some illustrative embodiments, the gate electrode material may be planarized, for instance, on the basis of CMP, to compensate for the highly non-uniform surface topography, when the gate electrode material is formed above the non-filled isolation trenches. Consequently, significant advantages of the mesa isolation strategy may be combined with a high degree of scalability due to the enhancement of the critical gate patterning process.

  Recently Added Patents
Owner-brokered knowledge sharing machine
Method and system for determining an optimal missile intercept approach direction for correct remote sensor-to-seeker handover
Head shield
Method of stimulating tissue healing
Secure device sharing
Semiconductor device manufacture in which minimum wiring pitch of connecting portion wiring layer is less than minimum wiring pitch of any other wiring layer
Cosmetic composition based on a supramolecular polymer and a hyperbranched functional polymer
  Randomly Featured Patents
Ram wing vehicle
Thermally reflective encapsulated phase change pigment
Process for preparing high molecular weight hydrophobic acrylamide polymers
Strainer assembly
Method of making microscope slide system
Wood planing machine with a wood shaving collecting mechanism
Factor IX moiety-polymer conjugates having a releasable linkage
Radio frequency semiconductor device
System and method for assigning symbolic names to data streams
Manufacturing method for compound semiconductor device