Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Method of enhancing lithography capabilities during gate formation in semiconductors having a pronounced surface topography










Image Number 6 for United States Patent #8101512.

In a mesa isolation configuration for forming a transistor on a semiconductor island, an additional planarization step is performed to enhance the uniformity of the gate patterning process. In some illustrative embodiments, the gate electrode material may be planarized, for instance, on the basis of CMP, to compensate for the highly non-uniform surface topography, when the gate electrode material is formed above the non-filled isolation trenches. Consequently, significant advantages of the mesa isolation strategy may be combined with a high degree of scalability due to the enhancement of the critical gate patterning process.








 
 
  Recently Added Patents
Thermoplastic resin composition
Systems, methods, and apparatus to determine physical location and routing within a field of low power beacons
Monitoring heap in real-time by a mobile agent to assess performance of virtual machine
Automated gate system
Medicament delivery device and a method of medicament delivery
Low powered activation arrangement and method thereof
Semiconductor device and fabrication method
  Randomly Featured Patents
Rotary throttle member and a throttle body for an internal combustion engine
Method of making a ceramic coated exhaust manifold and method
Data storage apparatus and access method thereof
Computationally intelligent agents for distributed intrusion detection system and method of practicing same
Acid sensor
Plant acclimatizing box
Image taking lens
Illumination apparatus, projector, and polarization conversion element
Piezoelectric transformer
Basketball