Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Method of enhancing lithography capabilities during gate formation in semiconductors having a pronounced surface topography










Image Number 6 for United States Patent #8101512.

In a mesa isolation configuration for forming a transistor on a semiconductor island, an additional planarization step is performed to enhance the uniformity of the gate patterning process. In some illustrative embodiments, the gate electrode material may be planarized, for instance, on the basis of CMP, to compensate for the highly non-uniform surface topography, when the gate electrode material is formed above the non-filled isolation trenches. Consequently, significant advantages of the mesa isolation strategy may be combined with a high degree of scalability due to the enhancement of the critical gate patterning process.








 
 
  Recently Added Patents
Photocurable composition and process for producing molded product having fine pattern on its surface
Integrated document viewer
Signal monitoring platform
Glucagon/GLP-1 receptor co-agonists
Flexible premium income annuity system and method
Range- and/or consumption calculation with energy costs associated with area segments
Lithographic method and apparatus
  Randomly Featured Patents
Laser irradiation method, method for manufacturing a semiconductor device, and a semiconductor device
Fly reel loader
Apparatus and method for providing a beacon signal in a wireless communication system
Digital timer with constant resolution
Cookware cover
Crosslinked polymer blends that include a luminescent polymer, and devices incorporating same
Compact storage shed
Method for geophysical processing and interpretation using seismic trace difference for analysis and display
Integrated power supply and platform for military radio
Protocol for authenticating functionality in a peripheral device