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System and method for reducing power consumption of a transistor-based circuit having multiple operational modes characterized by different power consumption level










Image Number 5 for United States Patent #8095809.

A method for reducing power consumption, and a system having power reduction capabilities, the method includes: storing, at a first circuit, data representative of a state of a second circuit, entering a low power mode, exiting low power mode, providing a default data value to the second circuit after exiting from the low power mode, and selectively providing data from the first circuit to the second circuit in response to the value of data and to a characteristic of a third circuit coupled to the first and second circuits.








 
 
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