Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Method for forming a vertical transistor having tensile layers










Image Number 4 for United States Patent #8093127.

A vertical transistor includes a semiconductor substrate provided with a pillar type active pattern over the surface thereof. A first tensile layer is formed over the semiconductor substrate and around the lower end portion of the pillar type active pattern, and a second tensile layer is formed over the upper end portion of the pillar type active pattern so that a tensile stress is applied in a vertical direction to the pillar type active pattern. A first junction region is formed within the surface of the semiconductor substrate below the first tensile layer and the pillar type active pattern. A gate is formed so as to surround at least a portion of the pillar type active pattern. A second junction region is formed within the upper end portion of the pillar type active pattern.








 
 
  Recently Added Patents
Color LED display device without color separation
Buffer pool extension for database server
Picture quality control method and image display using same
Toothbrush holder
Lamp body with integrally molded heat sink
Device in a system operating with CAN-protocol and in a control and/or supervision system
Methods and systems for enabling community-tested security features for legacy applications
  Randomly Featured Patents
Retractable assist grip and mounting method thereof
Frame for a storage drawer
Tool caddy
Heart rate change sensor
Macrolides and methods for producing same
Method for resetting a central lock system of a motor vehicle with a remote actuating device
Dual directional latch
Scissors with adjustable pivot
Speed ratio change control device and method for belt type continuously variable transmission
Perfluorocyclicamine, constant boiling composition and process for producing the same