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Method for forming a vertical transistor having tensile layers










Image Number 4 for United States Patent #8093127.

A vertical transistor includes a semiconductor substrate provided with a pillar type active pattern over the surface thereof. A first tensile layer is formed over the semiconductor substrate and around the lower end portion of the pillar type active pattern, and a second tensile layer is formed over the upper end portion of the pillar type active pattern so that a tensile stress is applied in a vertical direction to the pillar type active pattern. A first junction region is formed within the surface of the semiconductor substrate below the first tensile layer and the pillar type active pattern. A gate is formed so as to surround at least a portion of the pillar type active pattern. A second junction region is formed within the upper end portion of the pillar type active pattern.








 
 
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