Resources Contact Us Home
Integrated circuit device and associated layout including linear gate electrodes of different transistor types next to linear-shaped non-gate conductive segment

Image Number 15 for United States Patent #8089098.

A restricted layout region in a layout of a semiconductor device is disclosed to include a diffusion level layout including a plurality of diffusion region layout shapes. The plurality of diffusion region layout shapes are defined in a non-symmetrical manner relative to a centerline defined to bisect the diffusion level layout. A gate electrode level layout is defined to include linear-shaped layout features placed to extend in only a first parallel direction. Adjacent linear-shaped layout features that share a common line of extent in the first parallel direction are separated from each other by an end-to-end spacing that is substantially equal across the gate electrode level layout and that is minimized to an extent allowed by a semiconductor device manufacturing capability. The gate electrode level layout includes linear-shaped layout features defined along at least four different lines of extent in the first parallel direction.

  Recently Added Patents
Buck converter having reduced ripple under a light load
Business flow processing method and apparatus
Organic elelectroluminescent display
Battery grid
Distributed multicast packet replication with centralized quality of service
Utility knife
Method, apparatus, and system for synchronizing contents
  Randomly Featured Patents
Cable clamp and cable clamp assembly
Multiple local probe measuring device and method
Cart for fishing equipment
Projection apparatus with light source to output light into an integrating tunnel through a first and a second medium
Reversing preventing device
Handset telephone unit
Endoscope apparatus
Toughened prepregs and formulations
Solid electrolytic capacitor and method for manufacturing same
Event prediction