Resources Contact Us Home
Method for fabricating integrated circuit including separated diffusion regions of different type each having four gate electrodes with each of two complementary gate electrode pairs formed fr

Image Number 16 for United States Patent #8088681.

A cell layout of a semiconductor device includes a diffusion level layout including a plurality of diffusion region layout shapes, including p-type and n-type diffusion regions separated by a central inactive region. The cell layout also includes a gate electrode level layout for the entire cell defined to include linear-shaped layout features placed to extend in only a first parallel direction. Adjacent linear-shaped layout features that share a common line of extent in the first parallel direction are separated from each other by an end-to-end spacing that is substantially equal and minimized across the gate electrode level layout. Linear-shaped layout features within the gate electrode level layout extend over one or more of the p-type and/or n-type diffusion regions to form PMOS and NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the cell.

  Recently Added Patents
Headset electronics
Focusing apparatus that effectively sets a focus area of an image when a focusing mode is changed
Case for electronic device
Actuators and moveable elements with position sensing
Authenticated secret sharing
Case for electronic device
  Randomly Featured Patents
Method and apparatus for transforming a delivery container into a waste disposal system
Corrosion-preventing structure
Increased capacity reactor and its use
Gum and tooth brush
Optical sensor of physical magnitude
Curtain and window shade hardware
Heat dissipation device utilizing fan duct
Device for producing a reducing agent/exhaust gas mixture and exhaust gas purification system
Channelized stratified regenerator system and method
Battery terminal connector