Resources Contact Us Home
Method for fabricating integrated circuit including separated diffusion regions of different type each having four gate electrodes with each of two complementary gate electrode pairs formed fr

Image Number 16 for United States Patent #8088681.

A cell layout of a semiconductor device includes a diffusion level layout including a plurality of diffusion region layout shapes, including p-type and n-type diffusion regions separated by a central inactive region. The cell layout also includes a gate electrode level layout for the entire cell defined to include linear-shaped layout features placed to extend in only a first parallel direction. Adjacent linear-shaped layout features that share a common line of extent in the first parallel direction are separated from each other by an end-to-end spacing that is substantially equal and minimized across the gate electrode level layout. Linear-shaped layout features within the gate electrode level layout extend over one or more of the p-type and/or n-type diffusion regions to form PMOS and NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the cell.

  Recently Added Patents
Nano-pigment inkjet ink composition that has a low odor and is environmentally-friendly
Reduced plating ignitron
Method of using N-thio compounds for oligonucleotide synthesis
Boundary acoustic wave device
Controller with screen
Software execution management apparatus, method, and computer-readable medium thereof
Information processing apparatus, information outputting method and computer program storage device
  Randomly Featured Patents
Slot machine hybrid pin and ball game
Superconductors Bi-Sr-Cu-O
Imaging lens
Sensors for selectively determining liquid-phase or gas-phase components using a heteropolysiloxane sensitive layer
Polymer encapsulated electrical devices
Method and apparatus for conditional response to a fault condition in a switching power supply
Device for color distinction
Chicken mid-wing splitter
Base for a computer display
Coating method and composition using cationic photoinitiators polythio components and polyolefin components