Resources Contact Us Home
Method of manufacturing semiconductor device and semiconductor device

Image Number 12 for United States Patent #8084340.

A method of manufacturing a semiconductor device whereby, even in cases where ions are implanted into a shallow region of a semiconductor substrate when a deep well is formed, the influence of the ions on a MOSFET can be removed, thereby eliminating the need for increasing the chip area. A photoresist with a thickness matching the wavelength of exposure light is formed over the semiconductor substrate and then is exposed to the exposure light to form a photoresist pattern with an opening corresponding to a region for forming a first well. Subsequently, using the photoresist pattern as a mask, ions are implanted to form the first well, and after the photoresist pattern is removed, an epitaxial layer is grown over the semiconductor substrate. Consequently, the deep well is virtually located deeper in level than at the time of the ion implantation by an amount corresponding to the thickness of the epitaxial layer.

  Recently Added Patents
Analog-to-digital converter with input voltage biasing DC level of resonant oscillator
Providing user interfaces and window previews for hosted applications
Maesa japonica extracts and methods of use
Method and apparatus for compensating QoS during handover by base station in wireless broadband access system
Far field telemetry operations between an external device and an implantable medical device during recharge of the implantable medical device via a proximity coupling
Method for forming contact in an integrated circuit
Wireless refrigerant scale platform
  Randomly Featured Patents
IC card comprising a main device and an additional device
Sliding cover safety package
Door handle assembly
Time slot interchanger and digital communications terminal for ISDN D-channel assembly
Automatic guidance system for vehicles
Method for producing substrate to achieve semiconductor integrated circuits
Plasma display panel
Load cell attachment structure
Enclosure-based raid parity assist
Game console system capable of paralleling the operation of multiple graphic processing units (GPUS) employing a graphics hub device supported on a game console board