Resources Contact Us Home
Structure for inhibiting back end of line damage from dicing and chip packaging interaction failures

Image Number 13 for United States Patent #8076756.

A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.

  Recently Added Patents
Cordless hand blender
Nucleic acid sequences encoding strictosidine synthase proteins
Control device of hybrid vehicle
Gangable electrical box and leveling assembly
Positive electrode for secondary battery, and secondary battery
Systems and methods for advertising on content-screened web pages
Plants and seeds of hybrid corn variety CH260114
  Randomly Featured Patents
Non-destructive inspection apparatus and non-destructive inspection system
Pressure compensated fluid control valve
Method for enhancing the separation capacity of a multi-bed filtration system
Method and apparatus for adjusting tilting and level of optical signals
Controlled deployment delivery system
Electric reflector lamp
Support structure for a filter
Wire harness protector
Semiconductor device and method of manufacturing such a device