Resources Contact Us Home
Structure for inhibiting back end of line damage from dicing and chip packaging interaction failures

Image Number 13 for United States Patent #8076756.

A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.

  Recently Added Patents
High order continuous time filter
Secure provisioning of a portable device using a representation of a key
Method and system for migrating object update messages through synchronous data propagation
Light fitting
Semiconductor device
Circuitry for measuring and compensating phase and amplitude differences in NDT/NDI operation
Method for culturing lactic acid bacterium and method for producing fermented milk
  Randomly Featured Patents
Large-scale supply chain planning system and method
Printing head body for printer
Helical cutting
Manifold assembly for a gas range
Sheet processing device, image forming apparatus, and sheet processing method
Double brake protection device for elevator
Practice model for a tracheostomy
Method of decoking a cracking plant
Systems for the control and use of fluids and particles
Voltage regulator and data path for a memory device