Resources Contact Us Home
Structure for inhibiting back end of line damage from dicing and chip packaging interaction failures

Image Number 13 for United States Patent #8076756.

A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.

  Recently Added Patents
Liquid crystal display panel
Liquid crystal panel and liquid crystal display
System and method for access of user accounts on remote servers
Organic light emitting diode display device and method of fabricating the same
Radio transmitter and radio receiver with channel condition assessment
Making transparent capacitor with multi-layer grid
Dental fillers including a phosphorus containing surface treatment, and compositions and methods thereof
  Randomly Featured Patents
Polarity option control logic for use with a register of a programmable logic array macrocell
Moving object detection using a mobile infrared camera
Method and apparatus for base station transmitting broadcast multicast service(s) on traffic channel
Automatic slide-on panel loading system
Wireless headset
Safety brake system for a motor vehicle
Insurance policy revisioning method and apparatus
Data frame processing
Upper for a shoe
High density flip-flop with asynchronous reset