Resources Contact Us Home
Structure for inhibiting back end of line damage from dicing and chip packaging interaction failures

Image Number 13 for United States Patent #8076756.

A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.

  Recently Added Patents
Flavonoid dimers and methods of making and using such
Image browsing device, computer control method and information recording medium
Reliable event broadcaster with multiplexing and bandwidth control functions
Calendar integration methods and systems for presentation of events having combined activity and location information
Timing controller capable of removing surge signal and display apparatus including the same
Methods and systems providing desktop search capability to software application
Method and apparatus for focusing electrical stimulation in the brain during electro-convulsive therapy
  Randomly Featured Patents
Method of identifying engine cylinder combustion sequence based on combustion quality
Operation circuit for a work vehicle
Method of, and system for, adjusting a document configuration
Locking power transmitting device
Method for adjusting an electronic system
Process for efficiently concentrating an aroma stream
Process for preparing diphenylalkane
Method and apparatus for processing a substrate with minimal edge exclusion
DC-DC converter and transformer