Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Structure for inhibiting back end of line damage from dicing and chip packaging interaction failures










Image Number 13 for United States Patent #8076756.

A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.








 
 
  Recently Added Patents
High dynamic range pixel structure
Toy track intersection component
Methods and devices for creating, compressing and searching binary tree
System and method for performing image correction
Data output apparatus and data output method
Integrated bug tracking and testing
Computer implemented apparatus for generating and filtering creative proposal
  Randomly Featured Patents
Intelligent agents for electronic commerce
Advanced missile approach warning system (amaws) and stealth (low observables) detection based on exploitation of quantum effects
Revolving tray for breakfast cereal boxes
Keying waveform generator for spectrophotometer
Conduit bracket system
Vehicular lamp status display system
Vibrating gyroscope and electronic device using the same
High-resolution ion isolation utilizing broadband waveform signals
Hair treatment compositions
Position detector